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15 May 2001Ultrahigh-speed CMOS scanning linear imager family
A family of monochrome, high-speed linear imagers has been developed with each device to be available as a single chip fabricated using a standard commercially available CMOS process. Currently, the 2048 pixel device has been fabricated using a 0.5-micron CMOS process and its architecture, functionality and performance is described. The family of imagers features a unique combination of high functional integration, very high speed, low dark current, high sensitivity and high pixel-to-pixel uniformity. The pixels are 7.0 microns by 7.0 microns and have 100 percent fill factor. The high pixel-pixel uniformity is made possible by using low dark current pixels, a correlated double sampler circuit per pixel and a fully differential video bus. High functional integration is enabled by on-chip logic that is provided to minimize support circuitry and simplify application. Included are several exposure modes that provide full-frame electronic shutter, independent control of integration time and simultaneous integration and read-out. Only 5 volts DC and clock signal running at twice the desired pixel rate are required for basic operation. Low dark current and high sensitivity result from a novel pixel and low-noise preamplifier structure. A novel video multiplexing structure provides the very high read-out speed of 60 Mpixel/sec per 2048 pixel segment while sustaining an MTF of 50 percent at 35 line pairs per millimeter.
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Robert M. Iodice, Jeffrey J. Zarnowski, Matthew A. Pace, Michael Joyner, Thomas L. Vogelsong, Terry L. Zarnowski, "Ultrahigh-speed CMOS scanning linear imager family," Proc. SPIE 4306, Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications II, (15 May 2001); https://doi.org/10.1117/12.426946