29 December 2000 New programmable video signal processor for motion estimation and motion compensation
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A new programmable and parallel video signal processor (PVSP) is proposed to implement a class of fast block matching algorithms (BMA). Five parameters are used to embody the various fast BMAs and a generic framework for the fast BMA is designed. Then PVSP is designed and the BMA algorithms are mapped onto it. The key modules of PVSP are discussed in details. PVSP uses horizontal and vertical mapping strategies to implement byte-aligned and circular addressing. Under these two mapping strategies the memory system of PVSP can be configured flexibly. The regular, iterative and low-delay tree adder without any pipeline stages is chosen as the key computation component to implement the BMA. With scalable tree adder, PVSP can be easily expanded to meet higher computing requirement. PVSP is estimated to have approximately 30 kGates and 40 kb SRAM and it can work at the frequency of 133 MHz. It can support the motion estimation and motion compensation tasks in real-time for MPEG2 MPML encoder.
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Danian Gong, Danian Gong, Yun He, Yun He, } "New programmable video signal processor for motion estimation and motion compensation", Proc. SPIE 4310, Visual Communications and Image Processing 2001, (29 December 2000); doi: 10.1117/12.411875; https://doi.org/10.1117/12.411875

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