29 December 2000 VHDL design for hardware assistance of fractal image compression
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Abstract
Fractal image compression has several useful properties, including resolution independence, high compression ratios, rapid decoding, and subjectively good image quality. Despite this, its adoption has been limited, largely because of the very high computational burden of compression. In this paper, an original ASIC design is described which performs the comparisons required for fractal image compression of grayscale images. The design is based around a pipeline of many individual block comparison units through which the set of domain blocks are propagated. Each unit performs the required comparisons between a single range block and the series of domain blocks, and stores the best possible match. The ASIC is designed using synthesizable VHDL, allowing it to be targeted to virtually any digital technology. The small portions of the design which are specific to a particular application or technology, such as the bus interfaces and memory blocks, have been kept separate from the application- independent portions of the design. Simulations of the design suggests that an actual hardware implementation would be about one thousand times faster than a general purpose microprocessor based on similar IC technology, reducing the time required to optimally compress a 256 X 256 image using 8 X 8 range blocks from a few minutes to a fraction of a second.
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Andrew J. Erickson, Andrew J. Erickson, Muhammad E. Shaaban, Muhammad E. Shaaban, Kenneth W. Hsu, Kenneth W. Hsu, Roy S. Czernikowski, Roy S. Czernikowski, } "VHDL design for hardware assistance of fractal image compression", Proc. SPIE 4310, Visual Communications and Image Processing 2001, (29 December 2000); doi: 10.1117/12.411809; https://doi.org/10.1117/12.411809
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