22 August 2001 High-speed mapping of intertransistor overlay variations using active electrical metrology
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Abstract
Integrated circuits are becoming more sensitive to overlay errors between the most critical layers. This paper focuses on inter-transistor overlay variations, which are defined as the short-range variations of overlay between transistors separated by distances of 1 micrometers to 100 micrometers . Many circuits are particularly sensitive to these inter- transistor variations. However, inter-transistor variations are difficult to measure using conventional techniques of metrology. We have developed an active electrical metrology method using on-chip test circuitry to map inter-transistor overlay variations. Test chips were designed and fabricated on a commercial HP 0.35 micrometers process. An array of 127 x 64 active electrical overlay test structures was measured. The array has an area of 856.8 micrometers x 705.6 micrometers , with uniform sampling spacing of 6.8 micrometers x 11.2 micrometers . A measurement speed of 5 microsecond(s) per site was achieved with an accuracy of 6.5 nm (3-sigma). The measured overlay variations between gate poly and diffusion were found to be made up of alignment errors probably associated with the wafer stepper operation combined with short-range overlay variations probably contributed primarily by the mask. With 3-sigma values of 20-30 nm, the inter-transistor overlay variations are surprisingly large when viewed in the context of the typical overall overlay budget for a 0.35 micrometers process. Contour plots and Fourier analysis show that they have an obvious periodicity of 102.4 micrometers in y direction, which can be related to the writing stripes of the raster-scanned mask lithography system used to fabricate the masks. Intra- stripe and stripe-to-stripe overlay variations are then decomposed by spatial frequency filtering, and the intra- stripe variations are further analyzed.
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Xu Ouyang, C. Neil Berglund, Roger Fabian W. Pease, "High-speed mapping of intertransistor overlay variations using active electrical metrology", Proc. SPIE 4344, Metrology, Inspection, and Process Control for Microlithography XV, (22 August 2001); doi: 10.1117/12.436776; https://doi.org/10.1117/12.436776
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