Optimization of dielectric antireflective coatings on a transparent substrate in sub-half-micron CMOS technology

Graham G. Arthur; Brian Martin; Christine Wallace

doi:10.1117/12.436790

22 August 2001 Optimization of dielectric antireflective coatings on a transparent substrate in sub-half-micron CMOS technology

Graham G. Arthur, Brian Martin, Christine Wallace

Author Affiliations +

Proceedings Volume 4344, Metrology, Inspection, and Process Control for Microlithography XV; (2001) https://doi.org/10.1117/12.436790
Event: 26th Annual International Symposium on Microlithography, 2001, Santa Clara, CA, United States

Abstract

The optimization of a dielectric anti-reflective coating (ARC) on a transparent substrate with significant topography is described. Supporting theory is provided and although it is not possible to obtain the ultimate performance of an ARC over planar film stacks and flat substrates, the critical dimension (CD) swing ratio is greatly reduced and a manufactureable solution achieved using response surface modeling (RSM) in combination with data generated form the lithography simulation tool, PROLITH/2.

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Graham G. Arthur, Brian Martin, and Christine Wallace "Optimization of dielectric antireflective coatings on a transparent substrate in sub-half-micron CMOS technology", Proc. SPIE 4344, Metrology, Inspection, and Process Control for Microlithography XV, (22 August 2001); https://doi.org/10.1117/12.436790

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