22 August 2001 Sampling strategy and model to measure and compensate overlay errors
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Overlay is one of the key designed rules for producing VLSI devices. In order to have a better resolution and alignment accuracy in lithography process, it is important to model the overlay errors and then to compensate them into tolerances. This study aimed to develop a new model that bridges the gap between the existing theoretical models and the data obtained in real settings and to discuss the overlay sampling strategies with empirical data in a wafer fab. In addition, we used simulation to examine the relations between the various factors and the caused overlay errors. This paper concluded with discussions on further research.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chen-Fu Chien, Chen-Fu Chien, Kuo-Hao Chang, Kuo-Hao Chang, Chih-Ping Chen, Chih-Ping Chen, } "Sampling strategy and model to measure and compensate overlay errors", Proc. SPIE 4344, Metrology, Inspection, and Process Control for Microlithography XV, (22 August 2001); doi: 10.1117/12.436748; https://doi.org/10.1117/12.436748


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