Gate patterning has always been held to tight specifications for CD variation compared to other layers. Specifically, the gate layer is more concerned with the total CD variations including Across Chip Linewidth Variation (ACLV), Across Wafer Linewidth Variation (AWLV), CD variation through pitch (Proximity bias), than other layers. Therefore, complementary phase shift (c:PSM) imaging has been introduced at the gate layer under the assumption that it will reduce the total CD variation compared to binary imaging. However, c:PSM data conversion of random logic can introduce additional biases that also impact CD control. These new biases include CD variation as a function of shadow size, reticle-to-reticle overlay error, shifter width, and shifter height (a function of the transistor width and the shifter extension). This paper will show the improvements in ACLV and AWLV using c:PSM. This paper will also look at the increase in the proximity bias for c:PSM compared to binary imaging and show results for implementing a 1-D OPC correction on the phase shift reticle. In addition, this paper will also look at the magnitude of the various additional c:PSM biases mentioned. This paper will discuss the interaction of the different phase shift conversion input parameters for complex random logic and the limitations they impose on how tight we can make the final CD distribution. Finally, since c:PSM allows for selective sizing of CDs over active and over field, a brief discussion will also be given for the CD control of the complementary binary reticle.