A novel multiple resist patterning stacks (MURPAS) method has been applied on the copper, low-k dual damascene interconnection. Trench resist structures are directly patterned on the top of via resist layer without the resist interface intermixing using a cross-linked, high thermal resistance, negative-tone resist a the bottom via layer. A single etch step can transfer these integrated patterns into low-k substrate with a simplified resist stripping process and reduced risk of resist contamination to the low-k substrate. The gap-filling procedure for the positive-tone trench resist process, to avoid the via resist residue and the topography issue on the high aspect ratio via etched substrate, can be eliminated as the negative-tone trench resist in the via is not cross-linked and easy to be resolved. The interfield trench CD and trench profile uniformity can be consistently controlled since there is less process variation for the trench patterning. Overall, this integrated process requires a thinner resist thickness for the dual damascene pattern etch with an enlarged lithography process window for the resolution limit, mask error enhance factor, DOF, and line edge roughness for both via and trench lithography. Applications of MURPAS methods on double-exposure resolution enhanced technology (RET) such as the rectangular cell array and the aggressive assistant features for trench and hole patterns are also be studied.