14 September 2001 Patterning 80-nm gates using 248-nm lithography: an approach for 0.13-μm VLSI manufacturing
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Proceedings Volume 4346, Optical Microlithography XIV; (2001); doi: 10.1117/12.435745
Event: 26th Annual International Symposium on Microlithography, 2001, Santa Clara, CA, United States
Abstract
We have developed an 80nm poly gate patterning process for 0.13 micrometers VLSI manufacturing using 248nm lithography with double-exposure phase-shifting technique. We show that: Systematic intra-field line width variation can be controlled within 6nm (3(sigma) ), and total wafer variation across the wafer held to within 10nm (3(sigma) ), with good line-end shortening control for gate endcaps. The k1 factor is < 0.2 (80nm target gate length in 320nm pitch).
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Chien-Ming Wang, Chien-Wen Lai, Jason H. Huang, Hua-Yu Liu, "Patterning 80-nm gates using 248-nm lithography: an approach for 0.13-μm VLSI manufacturing", Proc. SPIE 4346, Optical Microlithography XIV, (14 September 2001); doi: 10.1117/12.435745; https://doi.org/10.1117/12.435745
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Photomasks

Semiconducting wafers

Binary data

Optical lithography

Lithography

Manufacturing

Phase shifts

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