26 July 2001 HiPAR-DSP 16: a new DSP for onboard real-time SAR systems
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Abstract
In this paper we present the HiPAR-DSP 16, a parallel and programmable processor architecture which is adapted to the demands of SAR image processing. TO provide a high performance, the HiPAR-DSP 16 features an array of 16 parallel processing units. Each of these processing units can process up to 3 instructions per clock cycle. Efficient data exchange between the processing units can be done by a shared memory with concurrent access. The HiPAR-DSP 16 is able to perform a 4096 samples complex FFT in 154 microsecond(s) and a compete (omega) k SAR processing algorithm on 4k range line with a PRF of more than 200 Hz in real-time. This shows the high capability of the HiPAR-DSP 16 for onboard real-time SAR systems.
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Helge Kloos, Lars Friebe, Jens Peter Wittenburg, Willm Hinrichs, Hanno Lieske, Peter Pirsch, "HiPAR-DSP 16: a new DSP for onboard real-time SAR systems", Proc. SPIE 4386, Photonic and Quantum Technologies for Aerospace Applications III, (26 July 2001); doi: 10.1117/12.434213; https://doi.org/10.1117/12.434213
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