26 April 2001 Analysis of full-wafer/full-batch CD uniformity using electrical linewidth measurements
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Proceedings Volume 4404, Lithography for Semiconductor Manufacturing II; (2001) https://doi.org/10.1117/12.425226
Event: Microelectronic and MEMS Technologies, 2001, Edinburgh, United Kingdom
A novel analysis methodology, for the breakdown and ranking of the different sources of line width variation, is presented. The method is applied both on the level of an individual wafer, and on multiple wafers in a batch. It enables evaluation of the exposure tool performance in relation to other contributors to line width variation. Separation of the contribution of the exposure tool component from other sources of line width errors, requires sufficiently dense and accurate sampling of the CD variation across a wafer, because of the statistical confidence needed in the budget breakdown analysis. These requirements are met by taking advantage of the excellent performance of Electrical Line Width Measurements in terms of repeatability and data acquisition speed. The exposure tool is found to be only responsible for a limited part of the total CD uniformity across the batch. The largest contributors are reticle and processing components at individual wafer level and the CD offset between the wafers at batch level. The resist process component is larger than expected due to a dominating swirl shaped artifact caus4ed by non optimal track performance. A refined analysis of the full wafer CD uniformity was focused on the systematic contributions from the H-V difference and scan direction. Both of these components appear to be only a small part of the intra die budget.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter Vanoppen, Peter Vanoppen, Oscar Noordman, Oscar Noordman, Jan Baselmans, Jan Baselmans, Jan B.P. van Schoot, Jan B.P. van Schoot, } "Analysis of full-wafer/full-batch CD uniformity using electrical linewidth measurements", Proc. SPIE 4404, Lithography for Semiconductor Manufacturing II, (26 April 2001); doi: 10.1117/12.425226; https://doi.org/10.1117/12.425226

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