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26 April 2001 Lithography aspects of dual-damascene interconnect technology
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Proceedings Volume 4404, Lithography for Semiconductor Manufacturing II; (2001) https://doi.org/10.1117/12.425203
Event: Microelectronic and MEMS Technologies, 2001, Edinburgh, United Kingdom
Abstract
The introduction of Cu and low-k dielectrics in back-end-of- line processes has serious implications for lithography. Different low-k material shave different reflective properties and also the potential use of hard masks has consequences for lithography. Furthermore, depending on the integration scheme that is chosen, various issues for lithography and etch are showing up. While the first photo step is on a planar substrate, the second photo has to cover a topography. This can have large implications on CD uniformity and the amount of material left for the subsequent etch.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mireille Maenhoudt, Diziana Van Goidsenhoven, Ivan K.A. Pollentier, Kurt G. Ronse, Muriel Lepage, Herbert Struyf, and Marleen Van Hove "Lithography aspects of dual-damascene interconnect technology", Proc. SPIE 4404, Lithography for Semiconductor Manufacturing II, (26 April 2001); https://doi.org/10.1117/12.425203
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