20 April 2001 20-μm deep trench isolation process characterization for linear bipolar ICs
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Proceedings Volume 4405, Process and Equipment Control in Microelectronic Manufacturing II; (2001) https://doi.org/10.1117/12.425246
Event: Microelectronic and MEMS Technologies, 2001, Edinburgh, United Kingdom
Abstract
The use of junction isolation in linear bipolar ICs substantially consumes silicon area. The replacement of junction isolation with trench isolation has the potential to significantly reduce device area while maintaining high voltage operation. Deep trench isolation has been implemented on a conventional non- complementary 40V (NPN BVceo) linear IC process. A fully functional lower power operational amplifier has been fabricated as a technology driver. Device characterization shows that transistor leakage currents (Iceo) and leakage between trench tubs can be made comparable with junction isolated devices. The NPN buried layer can successfully be butted against the trench sidewall without device degradation, although this is currently not possible with the NPN base. An NPN device shrink of 3X has been achieved and further development is underway to increase this towards the 4X level, where the base diffusion front touches the trench sidewall.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Terry Dyer, Ian J. Doohan, Martin Fallon, Dave McAlpine, Adam Aitkenhead, Jim McGinty, M. Taylor, Philip Gravelle, A. Schouten, M. Bryce, "20-μm deep trench isolation process characterization for linear bipolar ICs", Proc. SPIE 4405, Process and Equipment Control in Microelectronic Manufacturing II, (20 April 2001); doi: 10.1117/12.425246; https://doi.org/10.1117/12.425246
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