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23 April 2001 Failure analysis concepts for microelectronics technologies and manufacturing of the future
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The answer of Failure Analysis (F/A) to the technological innovations in microelectronics in the past was: with a slight evolution (i.e. optical microscope -- SEM -- TEM) we can do it. The innovations around the corner today enforce a paradigm shift in F/A to match the challenges by increasing wafer sizes, decreasing feature sizes and new package concepts. This presentation highlights various aspects of the small feature size time bomb (how TEM becomes mandatory and obsolete synchronously), the completely new inline F/A approach on productive wafers inevitable from 300 nm wafer size on, and the reinvention of electrical fail site localization techniques, now from the backside of the die due to new package concepts and innumerable metal layers. Even if F/A manages to overcome all these challenges from a technical point of view, the according revolution in terms of methods, skills and tools implies a cost explosion unless F/A becomes an active part in the business process and the projects of development and manufacturing. This holds even under the assumption that a rising number of today's F/A problems will be solved by modern testing techniques. Only this way F/A can deliver custom-tailored solutions that are optimized in productivity and time to result, and that fulfill the cost reduction requirements of semiconductor products.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Christian Boit, Rainer Weiland, A. Olbrich, U. Muehle, and B. Simmnacher "Failure analysis concepts for microelectronics technologies and manufacturing of the future", Proc. SPIE 4406, In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II, (23 April 2001);

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