23 April 2001 Wire-ball-bonding process evaluatiuon by using focused ion beam bondball characterization
Author Affiliations +
The adjustment of bonding parameters has been based for long time exclusively on the results of pull- and shear tests. Observing these parameters to be too low, bondparameters have been usually adjusted towards a stronger direction. FIB characterization, however, has shown, that in many cases pull forces have been at a low level, because the top chip metal layer (aluminum) has been completely consumed by the bondball- gold, forming a thick intermetallic phase with only weak adhesion to the barrier layer or intermetal dielectric. In these cases, reduction of the bonding parameters would be the suitable corrective action, whilst stronger adjustment results in cracking the silicon device or local cratering. Using different adjustments of bonding parameters, the point of optimum could be well found, corrected by the results of FIB- cross-sectional characterization. A good corresponding between cross-section analysis results and bonding process parameters has been found. It gives valuable hints on both process- homogeneity over the whole bonding length as well as on the optimum of the intermetallic layer thickness, which still should leave a continuous layer of chip metal. The border extremes show at one end of the process window local weak bonding and delamination lines, at the other end a completely consumed chip metallization. FIB characterization shows the bonding process influence on the grain structure of both wire and chip metallization, too.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter J. Jacob, Peter J. Jacob, Guenter Grossmann, Guenter Grossmann, Andreas Schertel, Andreas Schertel, Uwe Thiemann, Uwe Thiemann, } "Wire-ball-bonding process evaluatiuon by using focused ion beam bondball characterization", Proc. SPIE 4406, In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II, (23 April 2001); doi: 10.1117/12.425258; https://doi.org/10.1117/12.425258

Back to Top