For cost effective 130nm node manufacturing, it is prefer to use KrF binary chrome mask. To realize a production worth process for making random logic device, we need to effectively control mask error enhancement factor (MEEF) through pitch. In low k1 lithography, process parameters such as focus, lens aberration, linewidth, and line pitch, style of proximity correction (OPC), and resist process conditions, etc., all impact MEEF. We show a powerful RuMBa OPC method that can reduce MEEF to an acceptable level (close to 1(using KrF resist process. We believe that RuMBa OPC method can be further extended for sub 100nm ArF process. In wafer printing experiment, we have designed a new style of LineSweeper reticles for our lithography process optimization. Both simulated and printed wafer CD data were used to calculate the overlapped process window along with respective MEEF. These are the metric we used to assess the 130nm process performance. Using RuMBa OPC, we are able to achieve overlapped process window that is sufficient for 130nm gate mask process. The CD through pitch calibration is critical for an accurate model-based correct at location where OPC rule cannot cover. A high accuracy CD through pitch calibration methodology is developed for model calibration. In this paper, we have compared the 130nm performance using KrF binary mask, KrF 6% attenuated PSM, and ArF binary mask.