12 June 2001 Features of sorting memory realization
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Proceedings Volume 4425, Selected Papers from the International Conference on Optoelectronic Information Technologies; (2001) https://doi.org/10.1117/12.429701
Event: International Conference on Optoelectronic Information Technologies, 2000, Vinnytsia, Ukraine
Abstract
It is offered concept of the building high-performance linear- algebraic optoelectronic spatial processor for parallel processing the matrixes in system of the analysis of the scenes. The Processor realizes the arithmetic-logical operations of the parallel processing the matrixes, day set bit plane, as well as on their base scaling, tumbling, separation sidebar images. Happen to the results of the basic researches of the parallel mathematical models to organizations of the computing processes, algorithm and structures for algebraic adding, multiplying, division, matrix inversion. Their particularity there is removing the restrictions on dimensionality of the processed matrixes. They are evaluated main parameters proposed optoelectronic processor marketed on SEED-instrument. The Supposed level to capacity under digital accuracy of the calculations is found at a rate of 103 MFLOP.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
T. Martunyuk, T. Martunyuk, T. Vasilyeva, T. Vasilyeva, V. A. Suprigan, V. A. Suprigan, M. Al-Heyari, M. Al-Heyari, "Features of sorting memory realization", Proc. SPIE 4425, Selected Papers from the International Conference on Optoelectronic Information Technologies, (12 June 2001); doi: 10.1117/12.429701; https://doi.org/10.1117/12.429701
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