26 December 2001 Development of a configurable architecture for smart pixel research (CASPR)
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Abstract
The design, demonstration and evaluation of a general purpose, smart pixel based photonic information processing unit is presented. Based on a photonic VLSI device technology that can be implemented using a standard 1.5-micrometers CMOS, each pixel incorporates a photoreceiver with a RISC processor and produces a device that is suitable for prototyping photonic information processing systems.
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Prosenjit Mal, Prosenjit Mal, Jason Frederick Cantin, Jason Frederick Cantin, Fred Richard Beyette, Fred Richard Beyette, } "Development of a configurable architecture for smart pixel research (CASPR)", Proc. SPIE 4435, Wave Optics and VLSI Photonic Devices for Information Processing, (26 December 2001); doi: 10.1117/12.451152; https://doi.org/10.1117/12.451152
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