Interferometric metrology of wafer nanotopography for advanced CMOS process integration

John Francis Valley; Chris L. Koliopoulos; Shouhong Tang

doi:10.1117/12.450091

10 December 2001 Interferometric metrology of wafer nanotopography for advanced CMOS process integration

John Francis Valley, Chris L. Koliopoulos, Shouhong Tang

Proceedings Volume 4449, Optical Metrology Roadmap for the Semiconductor, Optical, and Data Storage Industries II; (2001) https://doi.org/10.1117/12.450091
Event: International Symposium on Optical Science and Technology, 2001, San Diego, CA, United States

Abstract

According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

Citation Download Citation

John Francis Valley, Chris L. Koliopoulos, and Shouhong Tang "Interferometric metrology of wafer nanotopography for advanced CMOS process integration", Proc. SPIE 4449, Optical Metrology Roadmap for the Semiconductor, Optical, and Data Storage Industries II, (10 December 2001); https://doi.org/10.1117/12.450091

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