Translator Disclaimer
13 December 2001 Low-latency optoelectronic processor-memory interconnection demonstrator
Author Affiliations +
Abstract
A principal performance limitation of current computers is memory access latency. The random access time of DRAM can be as low as 20 ns but the overhead imposed by communication latency can increase the retrieval time to 150 ns in single processor systems or 1 ms in large multiprocessor systems. Optically interconnected VLSI offers the possibility of reductions in the communication component of memory latency of an order of magnitude. The improvement arises from the potential of direct high bandwidth low-latency links between any one chip and each one of a set of others. This potential principally arises from the ease of an optical implementation of fan-out and fan-in operations, together with the intrinsically high bandwidth of optical links. We have designed a scaleable system of processor-memory interconnections to explore this technology. Optical fan-out and fan-in modules will link a single processor to a bank of memory chips. The approach allows for multiple processors to be connected to multiple memory banks in an analogous fashion. The demonstrator will use 1-D VCSEL and photodiode arrays to provide optical i/o for the CPU and memory chips. The optical fan-out, fan-in and image relay can be implemented using an integrated planar optical system.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Stuart J. Fancey, Juergen Jahns, Paul Lukowicz, and Janusz Grzyb "Low-latency optoelectronic processor-memory interconnection demonstrator", Proc. SPIE 4455, Micro- and Nano-optics for Optical Interconnection and Information Processing, (13 December 2001); https://doi.org/10.1117/12.450435
PROCEEDINGS
8 PAGES


SHARE
Advertisement
Advertisement
Back to Top