20 November 2001 Optimal design method for fast carry-skip adders
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A carry-skip adder is faster than a ripple carry adder and it has a simple structure. To maximize the speed it is necessary to optimize the width of the blocks that comprise the carry skip adder. This paper presents a simple algorithm to select the size of each block. Assuming that each logic gate has a unit delay, the algorithm achieves slightly faster designs for 64 and 128 bit adders than previous methods developed by Guyot, et al. and Kantabutra.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Songjun Lee, Songjun Lee, Earl E. Swartzlander, Earl E. Swartzlander, } "Optimal design method for fast carry-skip adders", Proc. SPIE 4474, Advanced Signal Processing Algorithms, Architectures, and Implementations XI, (20 November 2001); doi: 10.1117/12.448646; https://doi.org/10.1117/12.448646


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