24 July 2001 Reconfigurable processors for handhelds and wearables: application analysis
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Proceedings Volume 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III; (2001) https://doi.org/10.1117/12.434376
Event: ITCom 2001: International Symposium on the Convergence of IT and Communications, 2001, Denver, CO, United States
Abstract
In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.
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Rolf Enzler, Rolf Enzler, Marco Platzner, Marco Platzner, Christian Plessl, Christian Plessl, Lothar Thiele, Lothar Thiele, Gerhard Troester, Gerhard Troester, } "Reconfigurable processors for handhelds and wearables: application analysis", Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); doi: 10.1117/12.434376; https://doi.org/10.1117/12.434376
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