8 November 2001 Smart-pixel-based free-space interconnects: solving the high-speed multichip packaging bottleneck
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Proceedings Volume 4534, Optoelectronic and Wireless Data Management, Processing, Storage, and Retrieval; (2001) https://doi.org/10.1117/12.448005
Event: ITCom 2001: International Symposium on the Convergence of IT and Communications, 2001, Denver, CO, United States
As IC densities grow to 100's of millions of devices per chip and beyond, the inter-chip link bandwidth becomes a critical performance-limiting bottleneck in many applications. Electronic packaging technology has not kept pace with the growth of IC I/O requirements. Recent advances in smart pixel technology, however, offer the potential to use 3-D optical interconnects to overcome the inter-chip I/O bottleneck by linking dense arrays of Vertical Cavity Surface Emitting Lasers (VCSELs) and photodetectors, which are directly integrated onto electronic IC circuits. Many switching and parallel computing applications demand multi-chip interconnection fabrics that achieve high-density global I/O across an array of chips. Such global interconnections require a high degree of space-variance in the interconnection fabric, in addition to high inter-chip throughput capacity. This paper reviews the architectural and optical design issues associated with global interconnections among arrays of chips. The emphasis is on progress made in the design and implementation of the second generation Free-space Accelerator for Switching Terabit Networks (FAST-Net) prototype. The FAST-Net prototype uses a macro-optical lens array and mirror to effect a global (fully connected) fabric across a 4 X 4 array of smart pixel chips. Clusters of VCSELs and photodetectors are imaged onto corresponding clusters on other chips, creating a high- density bi-directional data path between every pair of smart pixel chips on a multi-chip module. The combination of programmable intra-chip electronic routing and the fixed global inter-chip optical interconnection pattern of the FAST- Net architecture has been shown to provide a low latency, minimum complexity fabric, that can effect an arbitrary interconnection pattern across the chip array. Recent experimental results show that the narrow beam characteristics of VCSELs can be exploited in an efficient optical design for the FAST-Net optical interconnection module. A new design combines micro-, mini-, and macro-optical elements to achieve the required high registration and resolution accuracy while minimizing the packaging and alignment complexity.
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Michael W. Haney, Michael W. Haney, Marc P. Christensen, Marc P. Christensen, Predrag Milojkovic, Predrag Milojkovic, Michael J. McFadden, Michael J. McFadden, } "Smart-pixel-based free-space interconnects: solving the high-speed multichip packaging bottleneck", Proc. SPIE 4534, Optoelectronic and Wireless Data Management, Processing, Storage, and Retrieval, (8 November 2001); doi: 10.1117/12.448005; https://doi.org/10.1117/12.448005

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