20 September 2001 IP core design of template matching algorithm in image processing
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Proceedings Volume 4555, Neural Network and Distributed Processing; (2001) https://doi.org/10.1117/12.441685
Event: Multispectral Image Processing and Pattern Recognition, 2001, Wuhan, China
Abstract
This paper presents the design and implementation of template matching IP cores for image processing. Enhanced Moment Preserving Pattern Matching (MPPM) algorithm of template matching was adopted for efficient hardware implementation. The cores were coded in Verilog HDL for modularity and portability. The IP cores were validated in a XC4052XL FPGA and XESS XS40 prototyping board.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Quanqing Zhu, Quanqing Zhu, Xuecheng Zou, Xuecheng Zou, Zhenzhong Dong, Zhenzhong Dong, Feng Huang, Feng Huang, Xubang Shen, Xubang Shen, } "IP core design of template matching algorithm in image processing", Proc. SPIE 4555, Neural Network and Distributed Processing, (20 September 2001); doi: 10.1117/12.441685; https://doi.org/10.1117/12.441685
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