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20 September 2001 Parallel algorithm implementation of MPEG-4 video decoder on DSP
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Proceedings Volume 4555, Neural Network and Distributed Processing; (2001) https://doi.org/10.1117/12.441690
Event: Multispectral Image Processing and Pattern Recognition, 2001, Wuhan, China
Abstract
MPEG-4 is an international coding standard that aims at providing standardized core technologies allowing efficient storage, transmission and manipulation of video data in multimedia environments. As mobility has become one of the key requirements of the information society today, the next generation mobile will be a service-oriented industry, capable of delivering rich multimedia content, especially streaming video, to the palms of mobile subscribers. MPEG-4, with its superior compression, interactivity and systems capabilities, is the most promising future standard. And that small package high performance high speed DSPs are very suitable to be used in portable devices. This paper describes the implementation of MPEG-4 SVP(simple visual profile) video decoder on the TMS320C6201 DSP which is on the 'C6x EVM evaluation module(EVM) . The Texas Instruments TMS320C62x devices are fixed-point DSPs that feature the VelociTiTM architecture, which is a high-performance, advanced, very-long-instruction-word (VLIW) architecture. With this architecture, a high degree of parallelism can be exploited to meet real-time requirements of video processing such as compression and decompression. In this paperú¼ different aspects of the decoder , the decoding algorithm, decoder structure and memory requirements are discussed.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Dongmei Li and Zhaohui Li "Parallel algorithm implementation of MPEG-4 video decoder on DSP", Proc. SPIE 4555, Neural Network and Distributed Processing, (20 September 2001); https://doi.org/10.1117/12.441690
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