2 October 2001 Packaging issues using FEA and experimental verification on a Si-based capacitive microrelay
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Proceedings Volume 4558, Reliability, Testing, and Characterization of MEMS/MOEMS; (2001) https://doi.org/10.1117/12.443005
Event: Micromachining and Microfabrication, 2001, San Francisco, CA, United States
Abstract
A Si based capacitive microrelay has been packaged in a premolded package and the packaging issues has been studied and verified by FEA and experimental methods. A quasi-3D finite element modeling has been used to understand the thin cap warpage on the microrelay under different process conditions. Experimental verification on the cap warpage showed that thermal loading is not the only contributing parameter for the cap warpage. A modified model with air loading effect and thermal loading effect validated the experimental result. Solution to overcome this problem has been studied with a hole in the package and reinforcement of cap with epoxy.
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C. S. Premachandran, C. S. Premachandran, Xiaowu Zhang, Xiaowu Zhang, T. C. Chai, T. C. Chai, Victor Samper, Victor Samper, T. B. Lim, T. B. Lim, } "Packaging issues using FEA and experimental verification on a Si-based capacitive microrelay", Proc. SPIE 4558, Reliability, Testing, and Characterization of MEMS/MOEMS, (2 October 2001); doi: 10.1117/12.443005; https://doi.org/10.1117/12.443005
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