Alternating phase shifting mask implementation to 0.1-um logic gates

Chung-Hsing Chang; San-De Tzu; Chen-Hao Hsieh; Chang-Min Dai; Burn Jeng Lin; Chia-Hui Lin; Hua-Yu Liu

doi:10.1117/12.458313

11 March 2002 Alternating phase shifting mask implementation to 0.1-μm logic gates

Chung-Hsing Chang, San-De Tzu, Chen-Hao Hsieh, Chang-Min Dai, Burn Jeng Lin, Chia-Hui Lin, Hua-Yu Liu

Author Affiliations +

Proceedings Volume 4562, 21st Annual BACUS Symposium on Photomask Technology; (2002) https://doi.org/10.1117/12.458313
Event: Photomask 2001, 2001, Monterey, CA, United States

Abstract

Double exposure alternating phase-shift mask (alt-PSM) technology with ArF exposure was used in the 0.1 micrometers technology node for patterning logic devices with polysilicon gates ranging from 110nm to 60nm. A dual-trench mask fabrication process was developed in-house at TSMC, and controls for phase accuracy and intensity balance were established. Optical proximity correction (OPC) was performed on both binary masks and alt-PSM. Interactions between the binary and the PSM exposures were taking in to accounted during the correction. Using Model based OPC and a single calibrated resist model, the critical dimensions (CD) linearity can be ideally matched to the designed CD for duty ratio >= 1:1.5 for polygate logic product has been implemented exhibiting an enlarged DOF, good resist line edge roughness (LER), a d CD uniformity.

Citation Download Citation

Chung-Hsing Chang, San-De Tzu, Chen-Hao Hsieh, Chang-Min Dai, Burn Jeng Lin, Chia-Hui Lin, and Hua-Yu Liu "Alternating phase shifting mask implementation to 0.1-μm logic gates", Proc. SPIE 4562, 21st Annual BACUS Symposium on Photomask Technology, (11 March 2002); https://doi.org/10.1117/12.458313

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