The main advantage of the double-exposure, alternating-aperture phase-shifting mask (AltPSM) technique is that a critical mask layer (e.g. poly gate) can be separated into two regions and the lithographic processes optimized for each separately. The most critical regions, the gates, are usually patterned by a dark-field AltPSM, as it provides the best patterning performance and CD-control for isolated and semi-dense gates. The less critical binary intensity mask defines the local interconnect lines and gate trim-out regions. However, as the technology rapidly moves into the sub-100 nm node and beyond, the local interconnects become critical as well. The binary trim mask will also need other resolution enhancement techniques (RET). RETs such as off-axis illumination (annular or quadrupole), in combination with optical proximity corrections (OPC), are required in order to improve process windows and CD-control on the interconnecting poly layer. These two masks require quite different lithography settings to achieve the optimum process performance for the 100-nm node. For example, while the AltPSM exposure will perform best under moderate or high numerical aperture (NA) and relatively low partial coherence, the trim mask patterning requires higher NA and higher partial coherence to resolve the 240nm pitches. At the same time, both masks show different optical proximity effects (OPE), which will require additional process optimization and correction by concurrently distributing OPC on the shifter and trim masks. In this paper, we present a full CMOS process optimization including illumination mode and proximity correction for both poly-layer images for the (sub-) 100nm node, using 193-nm lithography.