21 November 2001 ATM over SDH: design of a STM-16c transceiver using GaAs technology
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This paper describes an ATM transceiver implementation with add/drop function over SDH (Synchronous Digital Hierarchy) able to handle STM-16c (OC-48c) signals. The design has been developed using Vitesse HGaAs-IV technology using DCFL (Direct Coupled FET Logic) standard cells and obtaining, in this way, a logic gate level description which could be easily exportable to any technology.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Oscar Tubio, Oscar Tubio, Roberto Esper-Chain, Roberto Esper-Chain, Francisco Gonzalez, Francisco Gonzalez, Felix Tobajas, Felix Tobajas, Valentin de Armas, Valentin de Armas, Juan A. Montiel-Nelson, Juan A. Montiel-Nelson, Roberto Sarmiento, Roberto Sarmiento, } "ATM over SDH: design of a STM-16c transceiver using GaAs technology", Proc. SPIE 4591, Electronics and Structures for MEMS II, (21 November 2001); doi: 10.1117/12.449153; https://doi.org/10.1117/12.449153


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