21 November 2001 Single-crystal silicon nanostructure fabrication by scanning probe lithography and anisotropic wet etching
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Abstract
Silicon nanostructures have been demonstrated by electric- field-enhanced localized oxidation on single crystal silicon wafer using a scanning probe microscope (SPM). In this study, we have demonstrated the use of scanning probe lithography (SPL) and orientation-dependent etching (ODE) can easily obtain nano-wire and nano-gap down to 24nm and 60nm on (110)-oriented silicon substrate. The scanning probe lithography (SPL) provides high resolution, which can be adjusted by tip bias, tip set force, scanning speed, and ambient humidity of environment, without damage in the substrate. The etching process employed the orientation- dependent etching (ODE), because of the etching rate of the (111)-plane is slower than any other crystallographic planes such that anisotropic etching profile can be obtained. The experimental samples were hydrogen-passivated by dipping in 10% aqueous HF solution to remove sample native oxide on the surface before SPM localized oxidation process. The SiOx nano-patterns on (110)-oriented silicon substrate were generated by SPM localized oxidation. Then, the etching process employed the ODE with a 34 wt.% aqueous KOH solution. The nano-wire feature size is easily down to 24nm and aspect ratio larger than 4:1. The optimization line/space nanostructure is about 20nm/80nm and the nano-gap is about 60nm. In this study, we also have demonstrated the influence of etching temperature on the feature size of nanostructures with same aspect ratio. At the same etching depth (100nm), the line-width decreases with increasing the etching temperature. The theoretic etching rate and experimental etching rate are proportional to temperature, the higher temperature the higher etching rate.
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Kow-Ming Chang, Kai-Shyang You, Chia Haur Wu, Jeng Tzong Sheu, "Single-crystal silicon nanostructure fabrication by scanning probe lithography and anisotropic wet etching", Proc. SPIE 4592, Device and Process Technologies for MEMS and Microelectronics II, (21 November 2001); doi: 10.1117/12.448972; https://doi.org/10.1117/12.448972
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