16 October 2001 10-Gb/s 1:4 demultiplexer in 0.25-μm CMOS
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Proceedings Volume 4603, Fiber Optics and Optoelectronics for Network Applications; (2001) https://doi.org/10.1117/12.444544
Event: International Symposium on Optoelectonics and Microelectronics, 2001, Nanjing, China
Abstract
This paper described a 1:4 demultiplexer in a standard 0.25 micrometers CMOS. A tree-type structure is used to reduce the clock frequency and the SCL (Source Couple Logic) is used to construct high speed DFF. The chip occupies 1mm2 area. It consumes 683mW from a 3.3 V supply. The operating bit rates is higher than 10Gb/s.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Lei Tian, Lei Tian, Zhigong Wang, Zhigong Wang, Haitao Chen, Haitao Chen, Tingting Xie, Tingting Xie, Jianhua Lu, Jianhua Lu, Rui Tao, Rui Tao, Yi Dong, Yi Dong, Shizhong Xie, Shizhong Xie, } "10-Gb/s 1:4 demultiplexer in 0.25-μm CMOS", Proc. SPIE 4603, Fiber Optics and Optoelectronics for Network Applications, (16 October 2001); doi: 10.1117/12.444544; https://doi.org/10.1117/12.444544
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