24 July 2002 Effects of etching time and wafer miscut on the morphology of etched Si(111) surfaces
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Proceedings Volume 4608, Nanostructure Science, Metrology, and Technology; (2002) https://doi.org/10.1117/12.465124
Event: Workshop on Nanostructure Science, Metrology, and Technology, 2001, Gaithersburg, MD, United States
Abstract
Critical dimension metrology of silicon integrated circuit features at the sub-micrometer scale is an essential task in state-of-the-art semiconductor manufacturing. Determining the width of a feature or the scale in a pitch measurement with appropriate accuracy is consistently one of the most challenging elements of semiconductor metrology and manufacturing.
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Hui Zhou, Hui Zhou, Joseph Fu, Joseph Fu, Sotoshi Gonda, Sotoshi Gonda, Richard M. Silver, Richard M. Silver, "Effects of etching time and wafer miscut on the morphology of etched Si(111) surfaces", Proc. SPIE 4608, Nanostructure Science, Metrology, and Technology, (24 July 2002); doi: 10.1117/12.465124; https://doi.org/10.1117/12.465124
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