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21 May 2002 Optic fiber clock distribution in high-speed video memory
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Proceedings Volume 4650, Photodetector Materials and Devices VII; (2002)
Event: Symposium on Integrated Optoelectronic Devices, 2002, San Jose, California, United States
An electronic system based on a novel high-speed massive video memory array using an optical fiber clock distribution network has been investigated for the generation of random patterns for testing high-resolution color video monitors with screen sizes in the realm of 4096 by 4096 pixels. For frame rates in the range of 30 to 100 per second with 256 (28) to 4096 (212) intensity levels for each primary color the speed requirement amounts to 1.21x1010 to 6.04x1010 bits per second. The massive memory makes use of high-speed MSM photodetectors, optical receiver amplifiers and gallium arsenide charged coupled devices which are integrated on GaAs chips. These chips are assembled into 16 planes of multi-chip modules with 32 GaAs chips per plane. Only GaAs CCDs have been found to provide the short access times required to achieve the above data rates that exceed the capabilities of current silicon-based DRAMs. For proper operation clock skew must be eliminated, therefore, a 2-phase laser driven optical fiber distribution network has been considered. In addition, the photodetectors and amplifiers driving the CCDs must have speeds that do not compromise the access times of the CCD registers. To meet all requirements the design was implemented with optical fiber v-groove coupling to the MSM monolithic detectors and high-speed preamplifiers that are fabricated with the same technology as used for the fabrication of the CCDs.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter B. Kosel and Amir Amin Hanjani "Optic fiber clock distribution in high-speed video memory", Proc. SPIE 4650, Photodetector Materials and Devices VII, (21 May 2002);


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