3 June 2002 40-Gb/s 4 x 10 array VCSEL driver in 0.35-μm CMOS technology
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Proceedings Volume 4652, Optoelectronic Interconnects, Integrated Circuits, and Packaging; (2002) https://doi.org/10.1117/12.469570
Event: Symposium on Integrated Optoelectronic Devices, 2002, San Jose, California, United States
Abstract
In this paper, we present a 40 Gb/s VCSEL driver (4 x 10 channels, 1 Gbps/ch) designed and fabricated in HYNIX 0.35 micrometers 2-poly 4-matel CMOS technology. The CMOS driver designed for a free space optical interconnect system consists of two NMOS for driving a VCSEL and protection circuit rejecting influence of electrostatic discharge (ESD) or unexpected input signal with several tens voltage amplitude. Two NMOS with CMOS channel length of 0.4 micrometers and width of 100 micrometers are used for adjusting dc bias current from 0 to 27 mA and ac modulation current from 0 to 13.8 mA. Protection circuit is made of two diodes. The purpose of the protection circuit is to permit the input modulation voltage range only from -5 to 5 V.
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Hyung-Soo Kim, Hyung-Soo Kim, Sung-Jae Jung, Sung-Jae Jung, Hee-Hyun Lee, Hee-Hyun Lee, Doo-Gun Kim, Doo-Gun Kim, Young-Wan Choi, Young-Wan Choi, } "40-Gb/s 4 x 10 array VCSEL driver in 0.35-μm CMOS technology", Proc. SPIE 4652, Optoelectronic Interconnects, Integrated Circuits, and Packaging, (3 June 2002); doi: 10.1117/12.469570; https://doi.org/10.1117/12.469570
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