Optimized cladding materials for nonlinear-optic polymer-based devices

Mary Leovich; Perry P. Yaney; Cheng H. Zhang; William H. Steier; Min-Cheol Oh; Harold R. Fetterman; Alex K.Y. Jen; Larry Raymond Dalton; James G. Grote; Robert L. Nelson; John S. Zetts; Frank Kenneth Hopkins

doi:10.1117/12.469557

3 June 2002 Optimized cladding materials for nonlinear-optic polymer-based devices

Mary Leovich, Perry P. Yaney, Cheng H. Zhang, William H. Steier, Min-Cheol Oh, Harold R. Fetterman, Alex K.Y. Jen, Larry Raymond Dalton, James G. Grote, Robert L. Nelson, John S. Zetts, Frank Kenneth Hopkins

Author Affiliations +

Proceedings Volume 4652, Optoelectronic Interconnects, Integrated Circuits, and Packaging; (2002) https://doi.org/10.1117/12.469557
Event: Symposium on Integrated Optoelectronic Devices, 2002, San Jose, California, United States

Abstract

We have investigated various conductive and nonconductive polymer materials suitable for use as cladding layers in nonlinear optic (NLO) polymer based opto-electronic devices. Our goal was to maximize the nonlinearity of the NLO core materials, while minimizing the total poling voltage and minimizing the absorption loss. Using a cladding material that is more conductive than the NLO core material, the majority of the applied poling voltage is dropped across the core, realizing a maximum EO coefficient with minimum applied poling voltage. We found, however, that there are tradeoffs between absorption loss, conductivity, refractive index, materials processability and materials compatibility when using off-the-shelf materials. Results are presented for a 3-layer device structure using a conductive polymer material for both the top and bottom cladding layers.

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Mary Leovich, Perry P. Yaney, Cheng H. Zhang, William H. Steier, Min-Cheol Oh, Harold R. Fetterman, Alex K.Y. Jen, Larry Raymond Dalton, James G. Grote, Robert L. Nelson, John S. Zetts, and Frank Kenneth Hopkins "Optimized cladding materials for nonlinear-optic polymer-based devices", Proc. SPIE 4652, Optoelectronic Interconnects, Integrated Circuits, and Packaging, (3 June 2002); https://doi.org/10.1117/12.469557

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