Translator Disclaimer
24 April 2002 Column parallel vision system: CPV
Author Affiliations +
Abstract
We have designed and constructed a column parallel vision (CPV) system to realize an intelligent and general purpose image processing system with higher frame rate within 1 millisecond. The system consists of an original designed photo detector array (PDA) with high frame rate, a parallel processing unit with fully parallel processing elements (PEs), and a controller for PDA and PEs. The column parallel architecture enables the PDA 1 millisecond frame rate with 256 analog levels which is required for industrial image processing and measurements. The parallel processing unit has been fabricated by using FPGAs and has 128 X 128 PEs to perform the fully parallel image processing. The PEs have the S3PE architecture which has SIMD type parallel processing flow, and was constructed only 500 transistors suitable for integration in future. Since the PEs are operated by control signal from the controller, we can achieve desired image processing task to the system by changing the software. We have demonstrated that the system can be worked as a tracking system. The experimental results show the system was realized high speed feedback loop as 1000 frame/s including the tracking operation with noise reduction, matching (self-window algorithm) and moment calculation.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Naohisa Mukozaka, Haruyoshi Toyoda, Seiichiro Mizuno, Ming Hsien Wu, Yoshihiro Nakabo, and Masatoshi Ishikawa "Column parallel vision system: CPV", Proc. SPIE 4669, Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications III, (24 April 2002); https://doi.org/10.1117/12.463438
PROCEEDINGS
8 PAGES


SHARE
Advertisement
Advertisement
Back to Top