SDRAM bus schedule of HDTV video decoder

Hui Wang; Yan Li He; Lu Yu

doi:10.1117/12.451070

20 December 2001 SDRAM bus schedule of HDTV video decoder

Hui Wang, Yan Li He, Lu Yu

Proceedings Volume 4674, Media Processors 2002; (2001) https://doi.org/10.1117/12.451070
Event: Electronic Imaging, 2002, San Jose, California, United States

Abstract

In this paper, a time division multiplexed task scheduling (TDM) is designed for HDTV video decoder is proposed. There are three tasks: to fetch decoded data from SDRAM for displaying (DIS), read the reference data from SDRAM for motion compensating (REF) and write the motion compensated data back to SDRAM (WB) on the bus. The proposed schedule is based on the novel 4 banks interlaced SDRAM storage structure which results in less overhead on read/write time. Two SDRAM of 64M bits (4Bank×512K×32bit) are used. Compared with two banks, the four banks storage strategy read/write data with 45% less time. Therefore the process data rates for those three tasks are reduced. TDM is developed by round robin scheduling and fixed slot allocating. There are both MB slot and task slot. As a result the conflicts on bus are avoided, and the buffer size is reduced 48% compared with the priority bus scheduling. Moreover, there is a compacted bus schedule for the worst case of stuffing owning to the reduced executing time on tasks. The size of buffer is reduced and the control logic is simplified.

Citation Download Citation

Hui Wang, Yan Li He, and Lu Yu "SDRAM bus schedule of HDTV video decoder", Proc. SPIE 4674, Media Processors 2002, (20 December 2001); https://doi.org/10.1117/12.451070

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