16 July 2002 Die-scale wafer flatness: 3D imaging across 20 mm with nanometer-scale resolution
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Abstract
We present 3-dimensional atomic force profiler (AFP) measurements on die-scale flatness after copper and STI CMP. True metrology is achieved for patterned wafers. Wafers are vacuum-mounted on a flat chuck, as they would be in a stepper, so wafer warpage and strain-related non-planarity are not present. The results of this new technique are compared against current measurement techniques. For logic, memory and System-on-a-chip, we discuss the implications of wafer planarity going into subsequent photolithography steps.
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Kirk Miller, David H. Fong, Dean J. Dawson, Bradley Todd, "Die-scale wafer flatness: 3D imaging across 20 mm with nanometer-scale resolution", Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); doi: 10.1117/12.473527; https://doi.org/10.1117/12.473527
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KEYWORDS
Semiconducting wafers

Chemical mechanical planarization

Metrology

Copper

Image resolution

Logic

Optical lithography

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