Paper
16 July 2002 Evaluation of ASML ATHENA alignment system on Intel front-end processes
Graham M. Pugh, Maria Rebecca Giorgi
Author Affiliations +
Abstract
An evaluation of the ASML ATHENA alignment system was performed using marks placed in the scribeline of an Intel test chip used for 130 nm node processing. Exposures were performed using two ASML scanners at IMEC at the isolation, gate, contact and first metal layers, with extreme process splits performed at Intel at critical steps in between. The splits were arranged as factorials in order to evaluate the process sensitivity of the alignment system. The modeled overlay terms with the largest sensitivities are discussed. In addition, data taken by the scanners on various mark/recipe combinations is analyzed to provide insight into overlay optimization and potential alignment system limitations.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Graham M. Pugh and Maria Rebecca Giorgi "Evaluation of ASML ATHENA alignment system on Intel front-end processes", Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); https://doi.org/10.1117/12.473468
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CITATIONS
Cited by 3 scholarly publications.
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KEYWORDS
Semiconducting wafers

Optical alignment

Polishing

Scanners

Etching

Overlay metrology

Scanning probe microscopy

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