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16 July 2002 Overlay metrology results on leading-edge Cu processes
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As geometrical dimensions of semiconductor devices decrease, the need to introduce Cu processes into the fabrication cycle becomes increasingly important as a means of maintaining line resistances and circuit time constants. However, the success of implementing such as fabrication process is dependent on the ability to characterize it through quantitative means, such as Overlay metrology. In this paper we examine the overlay measurement results which have been obtained on a Cu based CMOS process at the 0.12 (Mu) m technology node. Overlay measurements were taken over a wide range of process conditions, and included wafers exhibiting extreme image contrast reversal, grainy conditions and low contrast. These factors have traditionally led to a decreased ability to make repeatable measurements, if the measurements could be made at all. Our results cover the important metrics of overlay metrology, and include precision, recipe portability, and measurement success rates. The results suggest that the overlay metrology issues encountered with such leading edge processes need not pose intractable barriers to obtaining reliable overlay metrology data.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Vincent Vachellerie, Delia Ristoiu, Alain G. Deleporte, Pierre-Olivier Sassoulas, Philippe Spinelli, Marc Poulingue, Pascal Fabre, Rolf Arendt, Ganesh Sundaram, and Paul C. Knutrud "Overlay metrology results on leading-edge Cu processes", Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002);

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