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24 July 2002 Integration of UTR processes into MPU IC manufacturing flows
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Low-k1 imaging, high-NA optics, pattern collapse, and the absorption of resist materials in 157-nm and EUV lithographies are driving down the thickness of the photoresist layer in integrated circuit fabrication processes. Although devices and test structures have been successfully fabricated with resist films thinner than 160 nm on various levels, the fabrication of working devices with high yield using ultrathin resist (UTR) integrations on multiple device layers has yet to be demonstrated. In the present work, gates have been patterned with 140-nm thick resist films with 10-15 defects per wafer, none of which are specific to the UTR process. Similar UTR gates were also patterned over 80-nm steps with no defects associated with the topography. The UTR NMOS transistors in this work have 10 pA/micrometers leakage and 400 (mu) A/micrometers drive currents, but the PMOS transistors do not perform as well. The line-edge roughness (LER) is 5-8 nm 3(sigma) depending upon exposure mask (binary vs. PSM) and substrate. Etching into 100 nm of crystalline Si reduces the LER to 4-7 nm 3(sigma) . The power spectral densities of the roughness have a Lorentzian shape, and most of the roughness occurs over length scales larger than 100 nm. Contact chains with electrical characteristics comparable to standard processes were fabricated with 120-nm thick resist films. Polysilicon as thick as 150 nm was etched successfully with 80-nm thick resist films and hardmasks.
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Jonathan L. Cobb, S. Dakshina-Murthy, Colita Parker, Eric Luckowski, Arturo M. Martinez Jr., Richard D. Peters, Wei Wu, and Scott Daniel Hector "Integration of UTR processes into MPU IC manufacturing flows", Proc. SPIE 4690, Advances in Resist Technology and Processing XIX, (24 July 2002);

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