As our chip producing industry gearing up for mass production of 130nm device technology node, use of EAPSM (Embedded Attenuated Phase Shift Mask) technology in the critical pattern levels became unavoidable because of the low k1 factor lithography involved. However, this 2-layer EAPSM material (attenuator material covered with Chrome) requires two distinctively separate lithography/etch processes needed to be carried out. These added complexities of processes are prone to degradation of the absorber material's (MoSi) sidewall leading to imperfect sidewall profiles (top corner rounding, off-normal sidewall angle, etching intrusion into quartz substrate, footing, . . . etc.). These imperfections of sidewall cause aerial image degradations thus reduce effectiveness of full benefits of PSM technology. In this paper, we discuss our findings of mask level aerial image degradation dependency on EAPSM material sidewall imperfections, which result from immature mask making processes, and assessments of its effects on pattern transfer onto wafer level using 3&2D EMF and subsequent lithography simulations. The results were then, compared to actual wafer results for the wafer level printing confirmation to the simulation results. We distinguish consequence of resulting aerial image differences between EMF simulations vs. Kirchhoff approximation (treatment of absorber to be infinitely thin layer; normally used in conventional lithography simulations) in the KrF EAPSM material (MoSi). Furthermore, we have carried out look-ahead assessments for ArF (193nm) lithography using ArF EAPSM material (MoSiON) and made association between the sidewall profile variations and CD uniformity performance of EAPSM. We will make case that 3D EMF capability consideration is important in the low k1 factor lithography simulations.