30 July 2002 Subresolution assist feature implementation for high-performance logic gate-level lithography
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Abstract
This paper investigates the implementation of sub-resolution assist features (SRAFs) in high performance logic designs for the poly-gate conductor level. We will discuss the concepts used for SRAF rule generation, SRAF data preparation and what we term "binary" optical proximity correction (OPC) to prevent catastrophic line-width problems. Lithographic process window (PW) data obtained with SRAFs will be compared to PW data obtained without SRAF. SRAM cells are shown printed with annular illumination and SRAFs, for both the 130 nm and 100 nm logic nodes as defined by the International Technology Roadmap for Semiconductors (ITRS). This study includes a comparison of the experimental results of SRAMs printed from designs corrected with rule-based OPC to those printed from designs corrected with model-based OPC.
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Allen H. Gabor, Allen H. Gabor, James A. Bruce, James A. Bruce, William Chu, William Chu, Richard A. Ferguson, Richard A. Ferguson, Carlos A. Fonseca, Carlos A. Fonseca, Ronald L. Gordon, Ronald L. Gordon, Kenneth R. Jantzen, Kenneth R. Jantzen, Mukesh Khare, Mukesh Khare, Mark A. Lavin, Mark A. Lavin, Woo-Hyeong Lee, Woo-Hyeong Lee, Lars W. Liebmann, Lars W. Liebmann, Karl Paul Muller, Karl Paul Muller, Jed H. Rankin, Jed H. Rankin, Patrick Varekamp, Patrick Varekamp, Franz X. Zach, Franz X. Zach, } "Subresolution assist feature implementation for high-performance logic gate-level lithography", Proc. SPIE 4691, Optical Microlithography XV, (30 July 2002); doi: 10.1117/12.474591; https://doi.org/10.1117/12.474591
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