The run-to-run control strategy of lithography APC is primarily composed of a feedback loop as shown in the diagram below. It is known that the insertion of a time delay in a feedback loop can cause degradation in control performance and could even cause a stable system to become unstable, if the time delay becomes sufficiently large. Many proponents of integrated metrology methods have cited the damage caused by metrology time delays as the primary justification for moving from a stand-alone to integrated metrology. While there is little dispute over the qualitative form of this argument, there has been very light published about the quantitative effects under real fab conditions - precisely how much control is lost due to these time delays. Another issue regarding time delays is that the length of these delays is not typically fixed - they vary from lot to lot and in some cases this variance can be large - from one hour on the short side to over 32 hours on the long side. Concern has been expressed that the variability in metrology time delays can cause undesirable dynamics in feedback loops that make it difficult to optimize feedback filters and gains and at worst could drive a system unstable. By using data from numerous fabs, spanning many sizes and styles of operation, we have conducted a quantitative study of the time delay effect on overlay run- to-run control. Our analysis resulted in the following conclusions: (1) There is a significant and material relationship between metrology time delay and overlay control under a variety of real world production conditions. (2) The run-to-run controller can be configured to minimize sensitivity to time delay variations. (3) The value of moving to integrated metrology can be quantified.

As progress in ultra-large scale integration (ULSI) continues to lower the critical dimension (CD) requirements, measurement science is regularly witnessing changes in the monitoring techniques for the development and control of semiconductor fabrication processes. Microscopy, reflectometry and ellipsometry are examples of optical techniques constantly adjusted in attempts to provide mask and wafer state monitoring with non-invasive, rapid and in situ schemes. In the past years special attention has been devoted to optical diffraction as a potential method to satisfy those requirements, yielding the field of scatterometry. A linearized method was introduced to represent the relationship between parameters that describe a surface relief profile and the resulting scattering geometry data. An advantage of this approach is that describe a surface relief profile and the resulting scatterometric data. An advantage of this approach is that large databases containing profile information are not needed to process the scatterometric dat, resulting in a technique that is more versatile to process changes. In this paper, studies on the effect of changing profile parameters as well as measurement variables on the accuracy of retrieved parameter values using the linearized inversion method are presented.

The 2001 Metrology Roadmap provides an overview of the challenges facing in-situ, in-line, and off-line measurement technology. As a part of the International Technology Roadmap for Semiconductors, the Metrology Roadmap is based on the process needs for Lithography, Front End Processes, on-chip Interconnect, and Packaging. The Metrology Roadmap also discuses the status and development needs for microscopy as an key need for all areas of measurement. The message from the ITRS Metrology Roadmap is that considerable development is needed for key process areas such as: the 3D critical dimensions for masks, transistor gates, and interconnect structures; the gate stack and ultra-shallow junctions; and interconnect materials stacks. The need for statically valid measurement that correlate to device and chip electrical properties is also emphasized. In this paper, the technical challenges found in the ITRS Metrology Roadmap and its potential solutions will be discussed.

Numerical calculation of angle-resolved light scattering characteristics of features with arbitrary shape, such as particle contaminations and surface defects, on a filmed surface is very useful to the development and calibration of wafer inspection tools. A model and associated code based on the discrete-dipole approximation used to compute the light scattering form a particle on a filmed surface is developed. The reflection interaction matrix is modified with the Sommerfeld integrals for filmed surfaces. 3D fast Fourier transform method is used for accelerating the computation. Model predicted scattering signatures for a 0.305 micrometers polystyrene latex sphere on a smooth thin layer of silicon dioxide film on silicon substrate are compared with experimental results. The incident beam has a wavelength of 632.8 nm and the incident angle is 70 degree. The comparison shows very good agreement between the modeling results and experimental results. The model is also checked with another numerical mode,, which further shows the validity of the model.

To be productive and profitable in a modern semiconductor fabrication environment, large amounts of manufacturing data must be collected, analyzed, and maintained. This data is increasingly being used to design new processes, control and maintain tools, and to provide the information needed for rapid yield learning and prediction. Towards this end, a significant level of investment has been made over the past decade to bring to maturity viable technologies for Automatic Defect Classification (ADC) as a means of automating the recognition and analysis of defect imagery captured during in-line inspection and off-line review. ADC has been developed to provide automation of the tedious manual inspection processes associated with defect review. Although significant advances have been achieved in the capabilities of ADC systems today, concerns continue to persist regarding effective integration, maintenance, and usability of commercial ADC technologies. During the summer of 2001, the Oak Ridge National Laboratory and International SEMATECH performed an industry survey of eight major semiconductor device manufacturers to address the issues of ADC integration, usability, and maintenance for the various in-line inspection and review applications available today. The purpose of the survey was to determine and prioritize those issues that inhibit the effective adoption, integration, and application of ADC technology in today's fabrication environment. In this paper, we will review the various ADC technologies available to the semiconductor industry today and discus the result of the survey.

Identification of particular defects plays a key role in achieving high yields for semiconductor device processing. This can be especially significant while developing and ramping new processes and technology nodes, and during efforts to recover from yield excursions. The detection of the particle's composition provides more definitive defect identification than an image alone, and greatly enhances the ability to find and eliminate the particle source. The challenges associated with particle identification become greater as the critical particle size decrease with each technology node. These challenges also become more important as new materials, new tools and new processes are introduced. Due to its surface sensitivity and high lateral spatial resolution, Auger analysis offers a unique capability for measuring the composition of very small, thin or complex particles. Auger analyses of particles that look alike sometimes reveal that they have very different compositions, and thus different defect sources. Auger readily provides compositional identification of thin surface contamination. A combination of Auger analysis with FIB cross-sections reveals the composition of buried particles and their relative position in the device stack.

This paper introduces a new non-referential defect detection (NRDD) algorithm for application to digital images of semiconductor wafers required during the manufacturing process. This new algorithm is composed to two major steps: (1) defect detection via the use of fractal image encoding and (2) enhanced defect boundary delineation using active contours. One primary application for this technology is the redetection of defects within archived databases of historical defect imagery. Defect images are commonly stored by semiconductor manufacturers for future diagnostic purposes, but reference images are usually unavailable. The ability to automatically redetect a defect is crucial in an automated diagnostic system that uses the historical defect images for defect sourcing. Results are presented for four large data sets of semiconductor images. Three of these data sets are composed of scanning-electron microscope (SEM) images and the fourth contains optical microscope images. Performance criteria were created that score the NRDD segmentation result as a percentage based on a comparison to a manually outlined version of the defect. The overall NRDD score across all four databases ranged from 50 percent to 84 percent using the same set of manually-determined parameters on all image within each database. By using an automated parameter setting algorithm these performance values improved to 57 percent to 92 percent. The NRDD algorithm performance depends, in part, on the size of the defect and the level of complexity of the background of the semiconductor image.

Residual metal inspection is an integral part of CMP manufacturing processes. This can be accomplished by adapting the existing YE inspection tools or microscopes. The use of Front Opening Unified Pod (FOUP) to house the wafers in 300 mm manufacturing offers unique challenges for wafer handling which necessitates the use of automated inspection procedures. These automated inspection procedures must not impede the flow of production material while achieving 100 percent inspection, and also have increased reliability compared to the existing inspection technologies. Ideally, these inspection procedures should be integrated into a feedback loop for further processing control. In this study, an existing particle monitoring technology for both bare and patterned wafers has been adapted for residual metal inspection. This is a new and unique application for post-metal CMP residue metal detection, which replaces the microscope visual inspection process. This technique uses a previously scanned 'golden wafer' to create the inspection recipe for a given pattern density and metal thickness, which is used to inspect other similarly processed product. This technique can be integrated to a CMP process tool, which can lead to significant reduction in cycle time and improved inspection efficiency.

This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

Historically for semiconductor processing, defects have been considered in a separate class as yield detractors and significant effort goes into detection, analysis and monitoring of defects. With the increase in complexity of nano technologies, defects now become a competent comprising only part of the overall picture of yield, or more importantly, of revenue. Given the acceleration decrease in feature sizes, there is a corresponding shift from emphasis on random defectivity to both systematical defectivity as well as parametric integrity. With the view that yield loss should be generalized to revenue loss of any type, it can then be understood that the notion of process monitoring generalizes to not just defect count, but also to be broader set of characteristic including device parameters. In this regards, the tool set for monitoring the process needs to be generalized to also include systematic and parametric inspection system. The model is that an inspection tool plus an associated algorithm is required for monitoring the variance in all critical elements. The fab must then optimize the set of tools and algorithms. Including integrated metrology tools in this optimization generalizes the revenue model further, but adds significant revenue enhancement opportunities. The issue and tradeoffs imply that the fabs must consider the full characterization needs in order to determine the proper mix of monitoring tools and algorithms.

A methodology is described which determines the kill rate of defects based on electrical testing using a short loop yield monitoring under conditions of low statistics. The results provide a quantitative means to rank the importance of defects as well as the effectiveness of the inspection strategy. Electrical test results form specifically designed test patterns for interconnect structures and correlated with optical defect inspection data to quantify the kill rates of various defects. A unique and important features of the approach is the use of deliberately introduced defects to study the impact at specific process points. The use of controlled defect inspection at each process step allows an improved statical analysis for low coverage inspection plans. The wafers are optically process step allows an improved statistical analysis for low coverage inspection plans. The wafers are optically inspected at all process steps and reviewed with an automated SEM. The defects are tracked and a defect Pareto is established. The defect management system provides direct correlations between electrical fails and optical defects. It appears that particles that occur at early stages in the process have an enhanced impact because of a potential size amplification effect. With the impact quantified, optimized inspection and defect reduction plans can be implemented.

The use of Decision Trees to analyze data is discussed as an approach to solving problems of Yield excursions in semiconductor manufacturing. The relation to equipment commonality is discussed along with some of the pitfalls of incautious use of general probability estimates. The paper introduces a Mixing Diagram to help visualize commonality issues, it introduces work around methods for resolving ambiguities in the commonality, it reviews Decision Trees algorithms, and it ends with a discussion of current limitations of the method along with recommendations for future research.

Images of semiconductor defects are maintained in semiconductor yield-management systems to help diagnose problems that arise during the manufacturing process. A common problem in future systems is the number of images to maintain, which is increasing at an alarming rate due to the growing use of in-line and off-line imaging systems. A manufacturing-specific content-based image retrieval system, or Automated Image Retrieval (AIR) system, was developed by ORNL in coordination with International SEMATECH during 1998-1999. The system uses commercial databases to store image information and uses a customized indexing technology to rapidly retrieve similar images base don visual content. In addition to acting as a yield management tool based on storing and retrieving images, the system can be utilized as a tool for data management by helping determine when images are redundant in relation to previously stored data. Ideally this information can be used to time-stamp the data for future purging based on a variety of ratings such as 'long- term', 'mid-term', and 'short-term'. In some situations the feedback from the AIR system can even be used to omit the image entirely based on pre-existing close matches. In this paper we explore techniques for using the AIR system to assist in image data management. Experimental results are shown with simulated image data representing various degrees of image clustering of redundancy, and manufacturing image data accumulated during earlier field-testing of the AIR system at industry sites. Early results indicate substantial reductions in the size of industry databases may be achievable while continuing to maintain an adequate representation and history of the manufacturing process. To reduce the number of stored images, AIR technology can be used in place of, or as a guide for, the typical 'store for N months and purge' approach to image management. This approach will enhance the use of the image database, since the real bottleneck in such a procedure is the need to sort such massive amounts of stored data as opposed to actual disk space.

We will discuss Advanced Micro Devices's (AMD) Fault Detection and Classification (FDC) program strategy and our six-step project template that we have identified that must be addressed for any successful FDC effort. We will discuss the recent development and implementation of a wafer-level FDC system on a TEL CLEAN TRAC ACT 8 photo track system in AMD's Fab25, a high volume microprocessor factory. We will present our approach to designing and implementing this FDC system and demonstrate its ability to automatically identify specific wafers within a lot that require manual review. Upon manual review, the decision can be made to rework the specific wafers or the lot.

With the introduction of 300 mm wafers to the ICS production line and the move to the 130 nm technology node, the requirements from individual tool and process modules become more critical when optimizing productivity and yield. For achieving top performance for the Fab, an 'Active control' is required. This 'Active control' system includes several components: Health Monitor, Fault Detection, Advanced Process Control (APC) and Data Mining. This paper describes these components of 'Active Control' and how they have been applied for advanced production on individual tools as well as on process modules. Controlling the individual tool by using Fault Detection uses a multivariate model that defines the tool's expected behavior for a specific recipe and gives an early warning on any possible deviation. The APC system also uses a sophisticated algorithm to provide dynamic fine- tuning of intermediate process targets that enhance final global targets. Fab wide systems will need to capture and retain relevant data: MES, defects, E-Test, yield, etc. With all these generated data, an advanced Data Mining system is needed to correlate process steps and tool information to yield and to correlate individual tool data down to a chamber level and end of the line yield.

One of the main challenges to implementations of traditional run-to-run control in the semiconductor industry is a high mix of products in a single factory. To address this challenge, Just-in-time Adaptive Disturbance Estimation (JADE) has been developed. JADE uses a recursive weighted least-squares parameters estimation technique to identify the contributions to variation that are dependent on product, as well as the tools on which the lot was processed. As applied to photolithography overlay, JADE assigns these sources of variation to contributions from the context items: tool, product, reference tool, and reference reticle. Simulations demonstrate that JADE effectively identifies disturbances in contributing context items when the variations are known to be additive. The superior performance of JADE over traditional EWMA is also shown in these simulations. The results of application of JADE to data from a high mix production facility show that JADE still performs better than EWMA, even with the challenges of a real manufacturing environment.

New 300mm facilities are decreasing start-up risks by developing new processes on 200mm equipment and transferring the process and manufacturing methods to the 300mm line. 200mm factories have stable processes, equipment and manufacturing methods. Leveraging a common Advanced Process Control (APC) architecture, both semiconductor manufacturers and equipment manufacturers have the ability to extend 200mm equipment capability, and transfer successful APC methods direct. Having a common tool-level APC on both 200mm and 300mm etch equipment, has proven valuable for TEL. Starting with fault detection and process control on 200mm equipment provides for rapid learning and qualification of the APC architecture and interfaces. When transferring the process and manufacturing methods that include APC to 300mm equipment, factories can efficiently ramp up new processes, and focus efforts in areas of high risk that need integrated fault detection. Etch process equipment provides the ultimate challenge due to the lack of physical process models. This requires extensive measurements of equipment and plasma state, followed by the development of empirical models to correlate equipment related state to the process state. The etch process requires chambers to be cleaned and consumable parts replaced, adding a large variable that must be included to make the models robust in high-volume manufacturing. Optimum productivity requires multiplexing 3 or 4 chambers running the same process. Chambers must produce matched process results, while allowing different clean cycles for flexibility of maintenance. Multivariate analysis, relating the equipment and plasma state to the wafer state, is required. A strategy that includes 200mm equipment in parallel with 300mm development supports customer legacy equipment improvements while providing a platform for 300mm APC applications that will extend pas current 200mm tool capability as new processes and manufacturing methods are developed. TEL's Etch APC product allows for equipment integration of real-time data, events, external sensors, and integrated metrology.

An investigation of the microloading effects form the 300mm wafer Etch and CMP polish processes was done at SC300, a joint venture between Motorola and Infineon Technologies for 300mm wafer, process and equipment development in Dresden, Germany. Test wafers were constructed to approximate the structural features of DRAM and microprocessors devices, and standard or scaled-up processes were run to identify potential limitations and defects. Oxide dielectric etch and CMP process instability and microloading effects are know n to cause significant device yield loss.

The purpose of this characterization was to gain an initial understand of the gate oxide integrity (GOI) differences on wafers processed in the 300mm furnace tools at SC300, a joint venture between Motorola and Infineon Technologies for 300mm wafer, process and equipment development, compared to similarly processed 200mm wafers at Motorola. Measurements were done using mercury probe tools located at different sites to characterize the various gate oxide films and thicknesses. Separately, a study was done on defectivity levels of the Epi-layered 300mm wafers used in this study.

At ultrahigh pressure the thermoelectric power, magneto resistance, and thermo magnetic effects were measured for Te, Se and S samples in the vicinity of semiconductor-metal phase boundary. The significant longitudinal and transverse Nernst-Ettingshausen effects observed for Te and Se allowed to estimate the scattering parameter for charge carriers. The increase of holes mobility obtained from longitudinal and transverse Nernst-Ettinghausen effects being consistent with growth of magneto resistance under pressure. These experiments gave configuration to decreasing of effective mass of holes at closing of direct semiconductor gap. From thermoelectric power measurements up to 40 GPa Sulfur was found to be a narrow-gap semiconductor with large negative pressure coefficient of electron gap. Negative magneto resistance effect observed in S suggests very low mobility of holes, that is in well agreement with retaining molecular type of crystal structure. Thermo magnetic effects, like galvanomagnetic ones, seems to be perspective for using in micro-device technology.

Timely detection and prevention of defect excursions is the primary goal of any yield enhancement methodology in a wafer processing fab. Contamination killer defects are traditionally at the focus of such efforts. However, systematic process-induced defects are increasingly impacting the yield in the contemporary manufacturing environment, which is characterized by rapid modifications, constantly decreasing design rules and narrowing process windows. While the treatment of killer random defects remains important, the emphasis on yield-limiting problems is shifting to subtle treatment of killer random defects remains important, the emphasis on yield-limiting problems is shifting to subtle precursor phenomena, before the tool yield is severally damaged. Common light-scattering inspection is limited when applied to early symptoms of process deterioration, such as defects below 100nm or those lying in trenches. Electrical defects are even more challenging, since in most cases they are entirely undetectable by optical means. Disconnected metal plugs, under-etch of contact and via holes, implant variations undetectable by optical means. Disconnected metal plugs, under-etch of contact and via holes, implant variations on active area, gate to active area shorts, junction leakage - all of them can produce an electrical signature that can be detected with electron beam microscopy using Voltage Contrast imaging. In this paper, we describe a methodology implemented at the STMicroelectronics fab in Crolles, France, that addresses the above issues. SEM reviews and discrete inspections with a SEMVision cX were used for characterization of a variety of optically invisible defects on several critical inspection steps: Shallow Trench Isolation after etch and CMP, Polysilicon after etch, Via after etch, Tungsten plugs after CMP, Aluminum metal lines after etch and Copper metal lines after CMP.

Industrial applications related to semiconductor wafer fabrication, such as Automatic Defect Classification (ADC), require reliable and rapid measurements of defect characteristics, typically within one second or less. Generally, ADC makes intensive use of 2D defect descriptors such as size or texture. Incorporation of 3D defect descriptors into the classifier can improve the ability to get a fast identification of the exact process step at which a given defect was introduced. Such 3D descriptors can be readily elucidated form a Defect Topographic Map (DTM), which holds the defect's complete 3D representation. In this paper, we introduce an approach for obtaining the DTM form a combination of a non-Lambertian reflectance function with a photometric stereo method (PSM), based on Multiple Perspective SEM Imaging. We also introduce a rapid map generation method based on the Fast Fourier Transform, which we name the Fourier Defect Topographic Map (FDTM). The FDTM exhibits good spatial performance as well as reduced computational requirements. Finally, we discus the detrimental effects of SEM material contrast effects on the generation of topographic maps. We show that effects such as shadowing and noise, can be readily overcome when using MPSI images, resulting in high-quality 3D defect representation.

A method for recording true holograms directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for dining defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep UV light.

Slicing semi-conductor wafers form ingots produces a damage layer that ha to be completely removed by complex polishing and etching processes. Nondestructively controlling the machining process is desirable. Laser induced surface acoustic waves are demonstrated to be a promising method to characterize the state of the surface.

0.7X reduction every two years, as required by Moore's Law, has increased the emphasis on low k1 imaging. Low k1 is a way to extend each wavelength one node. However, with low k1 imaging, a significant divide opens between the desires of the chip designer and the realities of lithographic reproduction. As k1 decreases from the safe and comfortable 0.8 value enjoyed in the 1980s, to the more stringent 0.5 adopted in production in the 90s, lithographers had to beg designers to let them do line biasing and place hammerheads at the ends of gates in order to compensate for simple proximity effects like iso-dense bias and line end shortening. Now, in the new millenium, many chip makers have to develop processes that work below 0.4 k1, which brings new tensions between the designer and the lithographer in the forms of design rule restrictions, 2D OPC, forbidden pitches, phase assignments, double exposure decompositions, etc.

Microprocessor product density and performance trends have continued to follow the course predicted by Moore's Law. To support the trends in the future and build logic products approaching one billion or more transistors before the end of the decade, several challenges must be met. These challenges include: (1) maintaining transistor/interconnect feature scaling, (2) the increasing power density dilemma, (3) increasing relative difficulty of 2D feature resolution and general critical dimension control, (4) identifying cost effective solutions to increasing process and design database complexity. The trend in transistor scaling can be maintained while addressing the power density issue with new transistor structures exemplified by the Depleted Substrate Transistor incorporating a raised source-drain and high-K gate dielectric. The general 2D patterning and resolution control problems will require several solution approaches both through design and technology e.g. reduce design degrees of freedom, use of simpler arrayed structures, improved uniformity, improved tools, etc. The data base complexity/cost problem will require solutions likely to involve use of improved data structure, improved use of hierarchy, and improved software and hardware solutions.

The likely possibility of having to support the 70 nm technology node with 193 nm lithography is lithography. The extremely significant resolution challenges and the ability of strong resolution enhancement techniques (RET) to meet them, is discussed. Evidence is presented that all strong RET impact the design flow by imposing nontrivial design restrictions. Data from an in-depth alternating phase shifted mask design feasibility assessment, conducted on the poly-gate level of the 180 nm technology node, is presented to give an outlook on the feasibility of RET-enabled design flows. Anticipated complications in taking such RET-enabled design flows to the complexity required for multiple critical levels of the 70nm node are discussed. An EDA solution focusing on complete integration of RET layout manipulations into the design flow is contrasted to an approach focusing on complex, optimized design rule comprises.

At its conception, 193 nm lithography was thought to be the best way to take optical lithography to the 180 nm node. It was expected that 193 nm could support the now-defunct 160 nm node before optical lithography would have to yield to an undetermined non-optical solution. Today, 193 nm must compete with 248 nm for the 130 nm node and is expected to support lithography until it is replaced by 157 nm at the 70 nm node. Given the challenges facing 157 nm, it is likely that lithographers will attempt to extend the utility of 193 nm to its theoretical limits.

Multiple exposure alternating phase-shifting mask lithography can exploit economies of scale to lower total manufacturing cost if chip designers adhere to simple rules, some of which also would apply to dipole illumination and other sub-wavelength lithography systems. The most promising system employs the Sidewall Chrome Alternating Aperture Mask structure which fulfills the theoretical expectations of strong phase-shift optics and offers the potential for low cost sub-100nm imaging with 248nm light. It has already printed 73nm semi-dense lines with 248nm light at k1 equals 0.19 and demonstrated a useful common processing window for less dense and isolated structures.

In this paper we review current design-to-silicon manufacturing challenges and complexities confronting the IC design and manufacturing worlds as the industry prepares for sub-100nm technology node IC production and discuss a simplifying infrastructure and various principles for reducing and managing these complexities. Rapidly increasing overall complexity spanning all elements of the design- through-silicon 'ecosystem' and entanglement of the intricacies of traditionally separable design and manufacturing process technical disciplines is increasingly evident in long-loop design-mask-FAB iterations portending a widening of the design-productivity gap and an impact on the cost-effectiveness and productivity of the IC industry. Using the concept of 'technology overshoot' we conclude that the IC industry must broaden its development efforts and diversify investments to include those of building a robust and inherently simplifying interface infrastructure between design and manufacturing and to enable the efficiencies required of a maturing industry. We also explore the concept of modularity and how other mature industries have employed it to optimize efficiencies and investments and conclude that while the design and manufacturing worlds have practiced a number of fundamental concepts of modularity - the overall desegregation of the industry as a whole as case in point - a consistent, well-planed architecture for managing the interface between the two worlds has not yet been employed; hindering the development and migration of much needed productivity and cost-effectiveness enhancements. We then discus the impact of these factors on the industry in light of sub-wavelength era lithography resolution enhancement technologies and related manufacturing process and device physics issue, which increasingly impact the design flow. Recognizing that significant improvement to the design-silicon manufacturing interface is required, lastly we discuss a solution in the form of a new industry initiative called GDS-3. In our findings we acknowledge that the IC industry has already developed a solution, called OpenAccess, to a similar problem in the design space having to do with interoperability between design automation tools. We relate this work to the issues being faced between design and manufacturability and draw our final conclusion that the new design-to-manufacturing infrastructure should be an augmentation of the design community's Open Access initiative.

The purpose of this paper is to name and discuss some of the most basic issues in today's optical microlithography and to promote consensuses building, helping with the emergence of a superior model-based WYSIWYG patterning paradigm.

RET treatments have become as integral a part of silicon manufacturing as steppers. For the 100-nm node, none of the critical layers can be adequately resolved without the application of at least one technique, and sometimes several in combination. All of these techniques can only be specified exactly in limited layout cases that are small enough for study and refinement. When the parameters defined in the initial study are applied to the full chip, however, the variability of real layout always leads to cases where the RET performs less than optimally. In fact, for most technqiues, the real layout imposes a balance between different layout needs. As an example, consider the use of off-axis illumination with sub-resolution assist features (SRAF). The illumination that performs ideally for the dense regions of the layout clearly does not work for all pitches thus the introduction of SRAF. Due to the limitations of infrastructure the SRAF assisted design is never an exact match to the dense reign the illumination is tuned for. The result is two-fold: one, the illumination must be relaxed in order not to be too selective of pitch, and the line width control across the chip becomes difficult. OPC and altPSM also both lead to the same two results when applied full chip.

Mask layouts with reticle enhancement techniques (RET) - including optical proximity correction (OPC), phase shift mask (PSM), Off-axis illumination, assist features (AF) - no longer closely resemble the design or wafer layouts. RET techniques are also applied with varying degrees of rigor to different portions of the layout, to constrain overall mask complexity while maintaining design requirements in critical areas. These factors make verifying RET mask layouts much more challenging. The simulation-based verification principle is straightforward: a wafer layout is simulated from the RET mask layout and compared to the intended design layout or 'target'. The required simulation technologies are mature and available today in commercial tools capable of handling large data files. The challenge in efficient verification is to establish comprehensive required for sub- wavelength lithography. Today, some simple criteria are inferred from the design or lithographic effects. Ideally, more specific information related to design 'intent' and tolerances should be built into the physical design for use in RET synthesis and verification, as well as in circuit and timing analysis. In this paper we explore emerging RET verification strategies that offer a high degree of flexibility and programmability. We will also illustrate how these techniques can take advantage of 'design intent' information embedded in the physical design, resulting in robust verification that is not confused by the complex tradeoffs required for today's sophisticated RET methodologies.

This paper presents the result of an extension to the concept of Micro-Yield modeling. We have developed a design attribute extraction and yield prediction software system that - given the characterization of a semiconductor process via complex test chips that we call Characterization Vehicle test chips and IC product layout and a set of proprietary yield models - computes detailed contributions of different yield models, of geometrical chip regions and of parts of the chip circuitry to the overall chip yield. The organization of the computed output allows easy comparison of predicted yields to inspection and electrical test measurements, where the electrical tests can include failure bit maps for memories and scan tests results for logic circuits. After we review the concept of the Yield Impact Matrix, we define a more general Micro-Event paradigm and introduce the Extended YIMP. We discuss its application to yield loss root-cause analysis, review related work and present example applications of the overall system built around this concepts.

In this paper, we propose a new analysis method to quantify the performance of optical proximity effect correction (OPC) as well as the gauge capability of in-process quality control (IPQC) monitors. The method consists of two stages. The first stage is to quantify the gauge capability of IPQC monitor patters for representing 'across chip line width variation' (ACLV). The second one is to verify OPC by using the IPQC monitor patterns as verified in the first stage. Our new analysis method has bene found to be remarkably effective and quite useful to optimize OPC parameters and other methods in attempting to reduce ACLV, the most critical factor in producing high-end logic devices with a design rule of 0.15 micrometers and below.

We describe a new procedure of design qualification to ensure manufacturability of deep sub-wavelength circuits. The procedure is based on optical simulation of the layout, integrated with device simulation of the layout, integrated with device simulation to meet predefined conditions set forth by the layout control lines called tolerance contours, a new concept proposed in this work, are first defined for active devices based on the geometry-dependent, target MOSFET parameters, such as I_ON and I_OFF and for interconnecting lines, based on the resolution of the etch process, misalignment and overlap or enclosure of metal and contact layers. Drawn geometries, OPC features, or exposure conditions are then adjusted such that the simulated silicon images would fall within the tolerance contours. The concept is demonstrated on SRAM cell shrink from 120 to 100 nm technology nodes.

This paper discusses the relationships between the design technology industry and other semiconductor supplier industries, against the backdrop of the semiconductor industry's overall technology requirements. The central claim is that 'design-process integration' is by no means blocked by lack of awareness of important problems; the key problems are well known. Rather, design technology currently faces too many more processing demands relative to its limited resources. This situation can improve only when the semiconductor industry and its supplier industries together adopt the perspective of 'sharing red bricks' i.e., identifying the most cost-effective and synergetic solutions to technology requirements form principle d analyses of cost and returns on investment.

In order to produce future generations of integrated circuits, it is advantageous to have a tighter coupling between process technology development and IC layout design. The first part of this paper describes a framework being developed in the TCAD area that facilitates such coupling. The second part of the paper provides examples of the coupling of design with one of the areas within TCAD, lithography simulation. The success of Optical Proximity Correction, for example, depends on accurate models that represent the lithography process, including photoresist performance. Some of the challenge sin developing accurate resist models are addresses. In addition to OPC and the short-range effects it addresses, the impact of long-range effects is also described. Two such effects are lens aberrations and flare, with the latter being particularly dependent on total layout.

The use of TCAD as a powerful tool for improving device performance and process manufacturability is describe din this paper. The ability for TCAD simulation to provide quick insight and understanding to better pMOS heavy doped drain extension design is illustrated. The impact of surface dielectric property and interface condition on the HDD diffusion profile, the transistor performance, and the transistor parametric variation is discussed through the use of SIMS profiles, simulation results, and silicon dat. Significant changes in HDD profile, transistor characteristics and parametric variability are attributed to surface oriented dopant diffusion. The severity of such changes can vary with varying surface dielectric properties. Through TCAD simulations, we postulate that the surface oriented dopant diffusion is mainly due to the existence of a super steep interstitial gradient (SSIG), in addition to SPE dopant transport effects. Monte Carlo implant simulations using UT-Marlowe and SIMS profiles how that higher-energy-lower-dose HDD implant would produce a better HDD diffusion profile of same junction depth than lower- energy-higher-dose HDD implant does, as a result of SSIG. SIMS experiments designed to reduce surface oriented diffusion by using Ge and F co-implant are discussed. The SIMS profiles show that Ge is able to reduce surface oriented dopant diffusion by steric effects, but F co- implant produces the best HDD profile.

Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, we seek to make a layout uniform with respect to prescribed density criteria, by inserting area fill geometries in to the layout. We review previous research on single-layer fill for flat and hierarchical layout density control based on the Interlevel Dielectric CMP model. We also describe the recent combination of CMP physical modeling and linear programing for multiple-layer density control, as well as the Shallow Trench Isolation CMP model. Our work makes the following contributions for the Multiple-layer Interlevel Dielectric CMP model. First, we propose a new linear programming approach with a new objective for the multiple-layer fill problem. Second, we describe modified Monte-Carlo approaches for the multiple- layer fill problem. Comparisons with previous approaches show that the new linear programming method is more reasonable for manufacturability, and that the Monte-Carlo approach is efficient and yields more accurate results for large layouts. The CMP step in Shallow Trench Isolation (STI) is a dual-material polishing process, i.e., multiple materials are being polished simultaneously during the CMP process. Simple greedy methods were proposed for the non- linear problem with Min-Var and Min-Fill objectives, where the certain amount of dummy features are always added at a position with the smallest density. In this paper, we propose more efficient Monte-Carlo methods for the Min-Var objective, as well a improved Greedy and Monte-Carlo methods for the Min-Fill objective. Our experimental experience shows that they can get better solutions with respect to the objectives.

In recent years, optical proximity correction (OPC) has become major technology to compensate the undesirable pattern distortions caused by systematic photolithography and etch variations. Model based OPC usually utilizes a scalar method to model diffraction limitations and coherence of optical system and empirical models to include etch variations. By calibrating the simulator to the experiential data from the focus exposure matrix (FEM) wafers, the lithography and etch errors can be predicted to some extent for 1D structures such as long lines and gaps. However, it has been difficult to predict the printability of such 2D patterns as line-ends, islands and small features with the simplified simulator. Furthermore, since the numerical aperture (NA) tends to increase in the state-of-the-art lithography and the wafer and mask topographies are becoming more complex, the optical simulator can no longer calculate aerial image correctly.

This paper validates the pattern matching methodology for locating and quantifying worst-case aberration-distortion of patterns through the comparison of theoretically predicted and simulated images. The matching process identifies those pattern element that will be most affected by the aberrations specific to the given lens. Once the highly impacted layout structures are identified, the region is extracted and simulated with and without aberrations using SPLAT to observe the induced pattern distortions. It is shown that even for good quality lenses, the resulting line- edge and line-end perturbations of PSM layouts for residual amounts of aberrations can exceed half those of optical proximity effects and may be quantified as additional input into the OPC process. The resulting feature edge shift is large and linear with aberration level for odd aberrations and much smaller for even aberrations whose electric fields add in quadrature. The effects of aberrations on binary marks are about half as large as the effects on phase-shift and phase-edge masks. The goal of the system is to allow measurements of aberrations across the field and among tools to be utilized int eh design process to inform designers of problematic features and to apply appropriate compensation on the mask.

After reviewing the normal approach to process window characterization and analysis used for a standard single exposure process, the applicability of that approach to a double exposure process is investigated. By properly designing the binary trim mask for a double exposure dark field alternating phase shift mask process, the influence of the trim exposure step on the final gate CD can be minimized. Flare during the rim exposure, however, is found to cause an undesired coupling of the two exposure steps. A method of accounting for this coupling effect for the gate CD process window is given.

When applying OPC techniques in manufacturing of complex and delicate integrated circuits, any improvement in accuracy of computing aerial images is crucial. Simulation accuracy is demanded more and more today as the feature sizes are being decrease, while the computation speed haw to be kept in a reasonable pace. As a consequence, loss of symmetry in simulation appears to be more problematic and has begun to require attention. Quantization, sampling and intensive iterative computation are all sources of the problem. In this paper, we study the problem of symmetry preservation, present method of symmetry enhancement, and apply the method in process simulation. The computing results of this method are satisfactory and promising, having laid a foundation for future study on its application in OPC, and of its effect on the performance of certain symmetric IC patterns.

Traditionally the design, layout, mask image and wafer image were considered to be equivalent. Effective modeling of the wafer image could be done with the assumption that the layout and mask had no impact on the predicted results. The ever-decreasing k₁ factor and the associated increase of reticle enhancement technology (RET) has changed all this. Optical proximity correction (OPC) causes the layout to no longer look like either the design or the desired wafer image. The acuity constraints of mask lithography further complicate the problem by limiting the information transfer between the layout and the reticle image. Two design methodologies have evolved to deal with mask acuity limitations. One approach is to exhaustively characterize the mask and its relationship with wafer imaging through iterative empirical techniques. This is too time consuming in the process development phase and treats the mask process as a 'black box', but it does drive to a reasonable cost mask solution. The other is to require mask of the highest acuity, which most accurately replicate the layout. This approach is faster in the process design phase but locks in the highest mask costs for the entire process life cycle. Both approaches are inflexible with regard to alternate mask source, either from different mask litho tools and processes or from different mask vendors.

A perspective is presented on how the semiconductor integrated circuit industry has evolved and what we can expect over the next decade or two. However, this 'forecast' is given in only the broadest sense, to make it relatively independent on innovations and discoveries that are likely to strongly shape the industry over this time period. Rather, trends are examined, as well as general 'tools' that will undoubtedly be important in advancing from our present microelectronics era to our presumable future in nanoelectronics.

We introduce a new cell architecture for Dynamic Random Access Memory (DRAM) and embedded DRAM applications. By exploiting the Floating Body characteristics of partially depleted silicon on insulator (SOI) transistors, a capacitor-less DRAM cell structure can store and amplify the stored signal by using only a single transistor. Such a DRAM cell has a footprint two times smaller than that of standard DRAM cells and can be integrated in any CMOS process.

The rise of low-k₁ optical lithography in IC manufacturing has introduced new questions concerning the physical and practical limits of particular sub-wavelength resoltuion-enhanced imaging approaches. For a given application tradeoffs between mask complexity design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only PSM approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k₁ < 0.3, thus enabling 90-nm node lithography with high-NA 248 nm exposure systems. We presents the results of experiments, simulations, and analysis designed to explore the tradeoffs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.

An exact formulation of the problem of imaging a 2D object through a Koehler illumination system is presented; the accurate simulation of a real layout is then not time- limited but memory-limited. The main idea behind the algorithm is that the boundary of the region that comprise a typical TCC Is made up of circular arcs, and therefore the area - which determines the value of the TCC - should be exactly computable in terms of elementary analytical functions. A change to integration around the boundary leads to an expression with minimal dependence on expensive functions such as arctangents and square roots. Numerical comparisons are made for a simple 2D structure.

The use of Resolution Enhancement Technologies (RET) is becoming mainstream for sub-wavelength lithography processes. Optical tools will not likely meet the process requirements for sub-130nm designs on their own. Different RET are being explored and in some cases, heavily used in order to improve the process window of sub-wavelength imaging. Model-based OPC, sub-resolution assist feature and phase shift masks are some of the most common RET Methods used to achieve production-worthy imaging. Every RET has its own limitations and advantages for every specific one. Some designs will not be able to be subjected to a specific RET because the layout is not friendly to it. Manual redesign of such layouts becomes intractable for very complex design with multiple cell attractive from the process integration point of view. By analysis standard cell libraries from an RET compliance attractive from the process integration point of view. By analysis standard cell libraries from an RET compliance perspective, it is possible to envision a methodology that can find the most RET-friendly design while maintaining the functional specification of every cell. This investigation focuses on sub-resolution assist features, alternating phase shift masks and double dipole. For most common RET approaches, minimum spacing, placement, width and feature geometry can be extracted from the RET compliance analysis. Later, a set of enhanced design rules that incorporate RET specific constraints is used to re-derive the optimal feature arrangement within the cells, until the cell meets the level of RET compliance defined by the user. Eventually, the process can be extended to ful layout compliance when all the interactions between individual cells is accounted for, and modified accordingly. The advantage of having RET compliant cell sis that during lace and route, the use can concentrate on optimizing global placement parameters instead of focusing on each individual cell. The final results will depend on the user requirements and acceptable parameters of ear, power, manufacturability, etc. This a general flow that is able to generate cells that meet electrical and manufacturing specifications and it is flexible enough to accommodate every existing RET.

Sub-resolution assist features (SRAF) have been demonstrated to provide significant process window improvement when used in combination with off-axis illumination (OAI) and attenuated phase shifted mask enhanced lithography. While some through pitch linewidth variations can be reduced through the use of SRAF, the main goal is to improve common process window, leaving the task of linewidth control to conventional optical proximity correction (OPC). OPC in combination with SRAF is also required to address 2D patterning infidelities such as corner rounding and line end shortening, for which SRAF do not provide adequate correction. Finally, OPC will be used as a means of recovering process window that may be lost in layout situations that result in poor SRAF coverage. With an industry wide migration form rules-based OPC to iterative, model-based solutions, the integration of inherently rules based SRAF generation and model-based OPC has to be investigated.

In this paper, we discuss rule-based and model-based tiling methodologies for interconnect layers and their implications for design flows and performance. The addition of these 'dummy' tiling metal features modifies the final physical design and reduces the variation of back-end process parameters. This is a newly developing area of design flow and its importance is increasing with each succeeding semiconductor generation. Along with this development new methodologies and tools need to be introduced to handle time placement post-physical design, as well as efficient methods for representing the resulting large amount of dat. Additionally, the inclusion of tiles may introduce performance-degrading parasitic effects. The situation is complicated by the order of the elements of the design flow: parasitics characterization requires knowledge about the placement of dummy metal times, which takes place after physical design. In this study, we co pare the advantages of having uniform interconnect characteristics to the performance degradation caused by the additional layout parasitics. We also discuss several possible scenarios for the modification of design flows to account for these effects the thereby recover timing and power targets closure. These scenarios depend for their success on the very different length scales of polish and electromagnetic effects. Finally, an analysis of correlations in the parameters that define design corners leads to the new conclusion that the negative effect of increased parasitic loading due to tiling is not as sever as a simple analysis would suggest. This result is due to the fact that the tiling parasitic loading is somewhat compensated for by the improved planarity resulting from tiling, which tightens the process variation-induced spread of metal electrical parameters.

As new resolution enhancement techniques (RETs) are adopted to progress beyond 100 nm, the costs and benefits to the overall system of data handling must be viewed as an overall system. A 'state' approach to viewing flows has been very useful for determining insertion points for several RETs. We examine insertion for OPC, MPC, and dipole illumination. Future improvements in data volume can come from two sources - data compression schemes, and hierarchy injection methods. Data compression gives a very rapid, one-time relief of 80 percent or more for flat data volume problems, but this gain only occurs once. Recognition of redundant cells and patterns in the layout and injecting hierarchy that eliminates this redundancy is an approach that rarely gives such large one-time gains, but can be applied over and over for many generations. We conclude with a creative suggestion for data management that aids data volume transmission problems while suggesting a new approach to the management of hierarchy.

Examining features of varying pitch imaged using phase- shifting masks shows a pitch dependence eon the transmission best suited for optimum imaging. The reason for this deals with the relative magnitude of the zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and 180- degree phase-shifted regions. Subsequently, some of the diffraction orders are collected and projected to form the image of the object. chromeless Phase-Shift Lithography (CPL) deals with using half-toning structures to manipulate these relative magnitudes of these diffraction orders to ultimately construct the desired projected image. A key feature of CPL is that with the ability to manipulate the diffraction orders, a single weak phase-shifting mask can be made to emulate any weak phase-shifting mask and therefore the optimal imaging condition of any pattern can be placed on a single mask regardless of the type of weak phase- shifter that produces that result. In addition, these structures are used to render the plurality of size, shape and pitch such that the formed images produce their respective desired size and shape with sufficient image process tolerance. These images are typically made under identical exposure conditions, but not limited to single exposure condition. These half toning structures can be used exterior, as assist features, or interior to the primary feature. These structures can range in transmission from 0 percent to 100 percent and they can be phase-shifted relative to the primary features or not. Thus CPL deals with the design, layout, and utilization of transparent and semi- transparent phase-shift masks and their use in an integrated imaging solution of exposure tool, mask and the photoresist recording media. This paper describes the method of diffraction matching, provides an example and reviews some experimental data using high numerical aperture KrF exposure.

Printing small geometries using wavelength of 248 nm on low- k materials is not a plug-in photolithography process from one technology to other technology node. In this paper, a method of film characterization of low-k dielectric materials will be discussed. For a characterization of chemical vapor deposited low-k dielectric materials, a positive tone deep UV (DUV) chemically amplified photoresist (CAR) was used as a poisoning gauge. In early development state of low-k dielectrics and copper dual damascene interconnects in back-end-of-line processes, unstable patterning behaviors were observed in spite of using an organic bottom antireflective coating layers on low-k substrates. The initial work was focused on finding the source of lot-to-lot critical dimension (CD) variations and understanding what causes this problem as well. Study indicated a strong correlation that photo CD depended on time interval between photolithography process and previous process step. Significant photo CD shift was introduced by short cycle time from thin film deposition to photolithography process and post via etch clean process to trench photolithography process. To minimize photo CD variations, the process optimizations were necessary in low- k dielectric film deposition, rework, via etch process, and post via etch clean process. As parallel efforts to improve lot-to-lot CD control, various photoresist system, different ambient annealing conditions, various surface organic and inorganic capping techniques were tested. In this experiments, time interval between processes was tightly controlled and maximized the worst case of scenario. Fresh and aged low-k dielectric films were analyzed using time-of- flight secondary ion mass spectrometry and x-ray photoelectron spectroscopy techniques. This work suggested that N2 containing in the film or introducing N2 into low-k dielectric film caused lot-ot-lot photo CD variations.

We have been exploring alternating aperture phase-shifting masks for Application Specific Integrated Circuit poly gate CD's below 100 nm. The implementation is dark field altPSM with a complementary bright field binary 'trim' mask. The alternating phase shift approach is attractive because of the potential for improved resolution, increased individual process windows, and reduced developed resist line edge roughening (LER) needed for superior device performance. This can be accomplished with moderately low exposure tool numerical aperture (NA). However, these improvements must justify the increased mask cost, throughput reduction of dual mask, and the necessity of optical and process pattern correction (OPC) of 2 masks. Compared to the single reticle non-strong phase shift approach, the altPSM option potentially has new modes of failure: image intensity imbalance between the 0 and 180 degree phases, phase error sensitivity, and quartz sidewall angle sensitivity, all as a function of feature p9itch. Additionally, the high coherence required to print altPSM sensitivities plus corrections for mask writing inaccuracies, lithography printing inaccuracies, and etch inhomogeneities. Manufacturing with altPSM adds additional CD uniformity requirements across the chip. In this paper we discuss the performance of a 193 nm altPSM dual mask set's printing across the exposure slit of an ASML/950 scanner in the 80 nm regime. We will show how wafer level image placement error varies with focus and pitch across the scanner slit. We will discuss 3 methods of OPC correction as a function of CD and pitch across the scanner slit, their self-agreement, and OPC grid requirements. We will also present OPC corrected common process windows across the slit.

Double-exposure techniques are currently being explored as alternatives to the low k₁ problem that arises form the current absence of next-generation lithography (NGL) tools. Off-axis illumination conditions such as annular, used in conjunction with binary chrome masks are able to resolve features as small as 100nm. However, these off-axis approaches only improve a limited set of pitches. While certain features on the layout are enhanced, others loose contrast and cannot be imaged properly. Dipole illumination is the extreme off-axis case, but this high/low contrast problem is lessened by a double exposure approach. Double exposure corrections require a global optimization of tow masks. As is the case with any multi-dimensional problem, current model OPC algorithms are able to locally optimize the solution, but it is difficult to guarantee a global optimal set. Including in the correction mask-manufacturing constraints can reduce this apparent problem. By limiting the number of local optimal states accessible to the convergence criterion, it is possible to arrive at a better solution. This solution is lithographically correct and easier to manufacture. In this work we preset a data flow using models created previously for a model-assisted dipole decomposition to rank different approaches based on final image contrast, pattern fidelity and focus dependency. We also provide insights on how angled features can be successfully imaged under a double dipole approach, showing how such features need to be studied form an image formation point of view, not under simple geometric principles that rule out the presence of angled features.

A design and verification methodology of advanced SRAM bitcell design is described. Dense bitcells, drawn for embedded SRAM memory applications, are drawn and simulated for cell functionality and stability. After first-pass design, lithography correction is determined using analytical and iterative simulation routines. Analytical corrections are tailored to comprehend not only specific tool and material platforms associated with the process technology, but are also optimized to account for process integration issues arising from mask layer to mask layer interactions. Lithography process windows are modeled though simulations based on specific stepper illumination scheme, and material systems. Process integration windows are modeled through overlay of simulated patterns while taking into account process control limits of misalignment and critical dimension. Comparison of simulated to electrical bitcell results are discussed and manufacturability considerations are addressed through electrical responses of bitcell-specific diagnostic test structures.

Dramatically increasing mask set costs, long-loop design-fabrication iterations, and lithography of unprecedented complexity and cost threaten to disrupt time-accepted IC industry progression as described by Moore’s Law. Practical and cost-effective IC manufacturing below the 100nm technology node presents significant and unique new challenges spanning multiple disciplines and overlapping traditionally separable components of the design-through-chip manufacturing flow. Lithographic and other process complexity is compounded by design, mask, and infrastructure technologies, which do not sufficiently account for increasingly stringent and complex manufacturing issues. Deep subwavelength and atomic-scale process and device physics effects increasingly invade and impact the design flow strongly at a time when the pressures for increased design productivity are escalating at a superlinear rate. Productivity gaps, both upstream in design and downstream in fabrication, are anticipated by many to increase due to dramatic increases in inherent complexity of the design-to-chip equation. Furthermore, the cost of lithographic equipment is increasing at an aggressive compound growth rate so large that we can no longer economically derive the benefit of the increased number of circuits per unit area unless we extend the life of lithographic equipment for more generations, and deeper into the subwavelength regime. Do these trends unambiguously lead to the conclusion that we need a revolution in design and design-process integration to enable the sub-100nm nodes? Or is such a premise similar to other well-known predictions of technology brick walls that never came true?