DESIGN, PROCESS INTEGRATION, AND CHARACTERIZATION FOR MICROELECTRONICS
7-8 March 2002
Santa Clara, CA, United States
Metrology for Process Characterization
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 1 (12 July 2002); doi: 10.1117/12.475656
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 17 (12 July 2002); doi: 10.1117/12.475665
Wafer Inspection
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 29 (12 July 2002); doi: 10.1117/12.475685
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 38 (12 July 2002); doi: 10.1117/12.475698
Defect Data Analysis
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 46 (12 July 2002); doi: 10.1117/12.475640
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 54 (12 July 2002); doi: 10.1117/12.475641
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 61 (12 July 2002); doi: 10.1117/12.475642
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Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 81 (12 July 2002); doi: 10.1117/12.475644
Yield Improvement and Analysis
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 88 (12 July 2002); doi: 10.1117/12.475645
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 100 (12 July 2002); doi: 10.1117/12.475646
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 112 (12 July 2002); doi: 10.1117/12.475647
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 120 (12 July 2002); doi: 10.1117/12.475648
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 128 (12 July 2002); doi: 10.1117/12.475649
Process Control and Characterization
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 136 (12 July 2002); doi: 10.1117/12.475650
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 147 (12 July 2002); doi: 10.1117/12.475651
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 155 (12 July 2002); doi: 10.1117/12.475652
Poster Session
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 212 (12 July 2002); doi: 10.1117/12.475653
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 223 (12 July 2002); doi: 10.1117/12.475654
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 235 (12 July 2002); doi: 10.1117/12.475655
Defect Data Analysis
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 162 (12 July 2002); doi: 10.1117/12.475657
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 168 (12 July 2002); doi: 10.1117/12.475658
Wafer Inspection
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 180 (12 July 2002); doi: 10.1117/12.475659
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 195 (12 July 2002); doi: 10.1117/12.475660
Integration: Enabling the Future
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 243 (12 July 2002); doi: 10.1117/12.475661
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 254 (12 July 2002); doi: 10.1117/12.475662
Advance RETs for 70 nm
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 262 (12 July 2002); doi: 10.1117/12.475663
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 274 (12 July 2002); doi: 10.1117/12.475664
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 288 (12 July 2002); doi: 10.1117/12.475666
Integration Methods II
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 566 (12 July 2002); doi: 10.1117/12.475667
Design Rules and Design Validation
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 312 (12 July 2002); doi: 10.1117/12.475668
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 328 (12 July 2002); doi: 10.1117/12.475669
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 336 (12 July 2002); doi: 10.1117/12.475670
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 345 (12 July 2002); doi: 10.1117/12.475671
Design Validation and ACLV
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 352 (12 July 2002); doi: 10.1117/12.475672
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 361 (12 July 2002); doi: 10.1117/12.475673
Integration Methods I
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 390 (12 July 2002); doi: 10.1117/12.475674
Technology Models and CAD I
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 405 (12 July 2002); doi: 10.1117/12.475675
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 411 (12 July 2002); doi: 10.1117/12.475676
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Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 444 (12 July 2002); doi: 10.1117/12.475679
Technology Models and CAD II
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 454 (12 July 2002); doi: 10.1117/12.475680
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 465 (12 July 2002); doi: 10.1117/12.475681
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 471 (12 July 2002); doi: 10.1117/12.475682
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 478 (12 July 2002); doi: 10.1117/12.475683
Devices and Patterning
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 489 (12 July 2002); doi: 10.1117/12.475684
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 503 (12 July 2002); doi: 10.1117/12.475686
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 517 (12 July 2002); doi: 10.1117/12.475687
Layouts and RETs
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 529 (12 July 2002); doi: 10.1117/12.475688
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 540 (12 July 2002); doi: 10.1117/12.475689
Integration Methods II
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 555 (12 July 2002); doi: 10.1117/12.475690
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 593 (12 July 2002); doi: 10.1117/12.475691
Advance RETs for 70 nm
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 298 (12 July 2002); doi: 10.1117/12.475692
Layouts and RETs
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 547 (12 July 2002); doi: 10.1117/12.475693
Design Validation and ACLV
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 379 (12 July 2002); doi: 10.1117/12.475694
Integration Methods II
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 585 (12 July 2002); doi: 10.1117/12.475695
Design Validation and ACLV
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 369 (12 July 2002); doi: 10.1117/12.475696
Panel Discussion: Do we need a revolution in design and process integration to enable sub-100 nm technology nodes?
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, pg 401 (12 July 2002); doi: 10.1117/12.475697
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