Chip-level line-width prediction methodology

Pat LaCour; Emile Y. Sahouria; Yuri Granik

doi:10.1117/12.475669

12 July 2002 Chip-level line-width prediction methodology

Pat LaCour, Emile Y. Sahouria, Yuri Granik

Proceedings Volume 4692, Design, Process Integration, and Characterization for Microelectronics; (2002) https://doi.org/10.1117/12.475669
Event: Design, Process Integration, and Characterization for Microelectronics, 2002, Santa Clara, CA, United States

Abstract

RET treatments have become as integral a part of silicon manufacturing as steppers. For the 100-nm node, none of the critical layers can be adequately resolved without the application of at least one technique, and sometimes several in combination. All of these techniques can only be specified exactly in limited layout cases that are small enough for study and refinement. When the parameters defined in the initial study are applied to the full chip, however, the variability of real layout always leads to cases where the RET performs less than optimally. In fact, for most technqiues, the real layout imposes a balance between different layout needs. As an example, consider the use of off-axis illumination with sub-resolution assist features (SRAF). The illumination that performs ideally for the dense regions of the layout clearly does not work for all pitches thus the introduction of SRAF. Due to the limitations of infrastructure the SRAF assisted design is never an exact match to the dense reign the illumination is tuned for. The result is two-fold: one, the illumination must be relaxed in order not to be too selective of pitch, and the line width control across the chip becomes difficult. OPC and altPSM also both lead to the same two results when applied full chip.

Citation Download Citation

Pat LaCour, Emile Y. Sahouria, and Yuri Granik "Chip-level line-width prediction methodology", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); https://doi.org/10.1117/12.475669

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