12 July 2002 Defect detection for short-loop process and SRAM-cell optimization by using addressable failure site-test structures (AFS-TS)
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Abstract
This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.
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Kelvin Yih-Yuh Doong, Kelvin Yih-Yuh Doong, Sunnys Hsieh, Sunnys Hsieh, S. C. Lin, S. C. Lin, J. R. Wang, J. R. Wang, Binson Shen, Binson Shen, L. J. Hung, L. J. Hung, J. C. Guo, J. C. Guo, I. C. Chen, I. C. Chen, K. L. Young, K. L. Young, Charles Ching-Hsiang Hsu, Charles Ching-Hsiang Hsu, } "Defect detection for short-loop process and SRAM-cell optimization by using addressable failure site-test structures (AFS-TS)", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475644; https://doi.org/10.1117/12.475644
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