12 July 2002 IC yield prediction and analysis using semi-empirical yield models and test data
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Abstract
This paper presents the result of an extension to the concept of Micro-Yield modeling. We have developed a design attribute extraction and yield prediction software system that - given the characterization of a semiconductor process via complex test chips that we call Characterization Vehicle test chips and IC product layout and a set of proprietary yield models - computes detailed contributions of different yield models, of geometrical chip regions and of parts of the chip circuitry to the overall chip yield. The organization of the computed output allows easy comparison of predicted yields to inspection and electrical test measurements, where the electrical tests can include failure bit maps for memories and scan tests results for logic circuits. After we review the concept of the Yield Impact Matrix, we define a more general Micro-Event paradigm and introduce the Extended YIMP. We discuss its application to yield loss root-cause analysis, review related work and present example applications of the overall system built around this concepts.
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Dennis J. Ciplickas, Mariusz Niewczas, Roland Ruehl, Brian Stine, Rakesh R. Vallishayee, Wojtek Wojciak, "IC yield prediction and analysis using semi-empirical yield models and test data", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475671; https://doi.org/10.1117/12.475671
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