Impact of subwavelength CD tolerance on device performance

Artur P. Balasinski; Linard Karklin; Valery Axelrad

doi:10.1117/12.475673

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12 July 2002 Impact of subwavelength CD tolerance on device performance

Artur P. Balasinski; Linard Karklin; Valery Axelrad

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Proceedings Volume 4692, Design, Process Integration, and Characterization for Microelectronics; (2002) https://doi.org/10.1117/12.475673
Event: Design, Process Integration, and Characterization for Microelectronics, 2002, Santa Clara, CA, United States

Abstract

We describe a new procedure of design qualification to ensure manufacturability of deep sub-wavelength circuits. The procedure is based on optical simulation of the layout, integrated with device simulation of the layout, integrated with device simulation to meet predefined conditions set forth by the layout control lines called tolerance contours, a new concept proposed in this work, are first defined for active devices based on the geometry-dependent, target MOSFET parameters, such as I_ON and I_OFF and for interconnecting lines, based on the resolution of the etch process, misalignment and overlap or enclosure of metal and contact layers. Drawn geometries, OPC features, or exposure conditions are then adjusted such that the simulated silicon images would fall within the tolerance contours. The concept is demonstrated on SRAM cell shrink from 120 to 100 nm technology nodes.

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Artur P. Balasinski, Linard Karklin, and Valery Axelrad "Impact of subwavelength CD tolerance on device performance", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); https://doi.org/10.1117/12.475673

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