12 July 2002 Panel discussion summary: do we need a revolution in design and process integration to enable sub-100-nm technology nodes?
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Dramatically increasing mask set costs, long-loop design-fabrication iterations, and lithography of unprecedented complexity and cost threaten to disrupt time-accepted IC industry progression as described by Moore’s Law. Practical and cost-effective IC manufacturing below the 100nm technology node presents significant and unique new challenges spanning multiple disciplines and overlapping traditionally separable components of the design-through-chip manufacturing flow. Lithographic and other process complexity is compounded by design, mask, and infrastructure technologies, which do not sufficiently account for increasingly stringent and complex manufacturing issues. Deep subwavelength and atomic-scale process and device physics effects increasingly invade and impact the design flow strongly at a time when the pressures for increased design productivity are escalating at a superlinear rate. Productivity gaps, both upstream in design and downstream in fabrication, are anticipated by many to increase due to dramatic increases in inherent complexity of the design-to-chip equation. Furthermore, the cost of lithographic equipment is increasing at an aggressive compound growth rate so large that we can no longer economically derive the benefit of the increased number of circuits per unit area unless we extend the life of lithographic equipment for more generations, and deeper into the subwavelength regime. Do these trends unambiguously lead to the conclusion that we need a revolution in design and design-process integration to enable the sub-100nm nodes? Or is such a premise similar to other well-known predictions of technology brick walls that never came true?
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Warren D. Grobman, Warren D. Grobman, } "Panel discussion summary: do we need a revolution in design and process integration to enable sub-100-nm technology nodes?", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475697; https://doi.org/10.1117/12.475697

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